75 lines
3.0 KiB
Verilog
75 lines
3.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2017(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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module cic_int #(
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parameter DATA_WIDTH = 12,
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parameter STAGE_WIDTH = 1,
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parameter NUM_STAGES = 1
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) (
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input clk,
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input [NUM_STAGES-1:0] ce,
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input [DATA_WIDTH-1:0] data_in,
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output [DATA_WIDTH-1:0] data_out
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);
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reg [DATA_WIDTH-1:0] state = 'h00;
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wire [DATA_WIDTH-1:0] sum;
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wire [DATA_WIDTH-1:0] mask;
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assign data_out = state;
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assign sum = (data_in & mask) + (state & mask);
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generate
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genvar i;
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for (i = 0; i < NUM_STAGES; i = i + 1) begin
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localparam j = NUM_STAGES - i - 1;
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localparam H = DATA_WIDTH - STAGE_WIDTH * i - 1;
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localparam L = j == 0 ? 0 : DATA_WIDTH - STAGE_WIDTH * (i+1);
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assign mask[H:L] = {{H-L{1'b1}},j != 0 ? ce[j] : 1'b1};
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always @(posedge clk) begin
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if (ce[j] == 1'b1) begin
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state[H:L] <= sum[H:L];
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end
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end
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end
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endgenerate
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endmodule
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