e4c9c8734c
For most of the DACs that use JESD204 as the data transport the digital interface is very similar. They are mainly differentiated by number of JESD204 lanes, number of converter channels and number of bits per sample. Currently for each supported converter there exists a converter specific core which has the converter specific requirements hard-coded. Introduce a new generic core that has the number of lanes, number of channels and bits per sample as synthesis-time configurable parameters. It can be used as a drop-in replacement for the existing converter specific cores. This has the advantage of a shared and reduced code base. Code improvements will automatically be available for all converters and don't have to be manually ported to each core individually. It also makes it very easy to introduce support for new converters that follow the existing schema. Since the JESD204 framer is now procedurally generated it is also very easy to support board or application specific requirements where the lane to converter ratio differs from the default (E.g. use 2 lanes/2 converters instead of 4 lanes/2 converters). This new core is primarily based on the existing axi_ad9144. For the time being the core is not user instantiatable and will only be used as a based to re-implement the converter specific cores. It will be extended in the future to allow user instantiation. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
||
|---|---|---|
| .. | ||
| ad_ip_jesd204_tpl_adc | ||
| ad_ip_jesd204_tpl_dac | ||
| axi_jesd204_common | ||
| axi_jesd204_rx | ||
| axi_jesd204_tx | ||
| interfaces | ||
| jesd204_common | ||
| jesd204_rx | ||
| jesd204_rx_static_config | ||
| jesd204_soft_pcs_rx | ||
| jesd204_soft_pcs_tx | ||
| jesd204_tx | ||
| jesd204_tx_static_config | ||
| scripts | ||
| tb | ||
| README.md | ||
README.md
Analog Devices JESD204B HDL Support
Licensing
The ADI JESD204 Core is released under the following license, which is different than all other HDL cores in this repository.
Please read this, and understand the freedoms and responsibilities you have by using this source code/core.
The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
This core is free software, you can use run, copy, study, change, ask questions about and improve this core. Distribution of source, or resulting binaries (including those inside an FPGA or ASIC) require you to release the source of the entire project (excluding the system libraries provide by the tools/compiler/FPGA vendor). These are the terms of the GNU General Public License version 2 as published by the Free Software Foundation.
This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License version 2 along with this source code, and binary. If not, see http://www.gnu.org/licenses/.
Commercial licenses (with commercial support) of this JESD204 core are also available under terms different than the General Public License. (e.g. they do not require you to accompany any image (FPGA or ASIC) using the JESD204 core with any corresponding source code.) For these alternate terms you must purchase a license from Analog Devices Technology Licensing Office. Users interested in such a license should contact jesd204-licensing@analog.com for more information. This commercial license is sub-licensable (if you purchase chips from Analog Devices, incorporate them into your PCB level product, and purchase a JESD204 license, end users of your product will also have a license to use this core in a commercial setting without releasing their source code).
In addition, we kindly ask you to acknowledge ADI in any program, application or publication in which you use this JESD204 HDL core. (You are not required to do so; it is up to your common sense to decide whether you want to comply with this request or not.) For general publications, we suggest referencing : “The design and implementation of the JESD204 HDL Core used in this project is copyright © 2016-2017, Analog Devices, Inc.”
Support
Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via https://ez.analog.com/community/fpga under the GPL license. If you would like deterministic support when using this core with an ADI component, please investigate a commercial license. Using a non-ADI JESD204 device with this core is possible under the GPL, but Analog Devices will not help with issues you may encounter.