29e6bbde88
On Arria10 there are 6 transceivers in a single bank. If more than 6 transceivers are used these will end up in multiple banks. The ATX PLL can directly connect to the transceivers in the same bank through the 1x clock network. To connect to transceivers in another bank it has to go through a master clock generation block (MCGB) and the xN clock network. Add support for instantiating the MCGB if more than 6 lanes are used. In this case the first 6 transceivers will still have a direct connection to the PLL while all other transceivers will be clocked by the MCGB. Note that this requires that the first 6 transceivers are all in the same bank. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
||
|---|---|---|
| .. | ||
| adi_jesd204 | ||
| avl_adxcfg | ||
| avl_adxcvr | ||
| avl_adxcvr_octet_swap | ||
| avl_adxphy | ||
| avl_dacfifo | ||
| axi_adxcvr | ||
| common | ||
| jesd204_phy | ||