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dumitruceclan a23ed6f715 axi_logic_analyzer: Improve overwrite control logic 
1. Add intermediary data_src_select register to control output selection
 between DMA and RAW. The switch RAW->DMA is not made until DMA has valid
 data; the switch DMA->RAW is not made until overwrite_enable is 1
 regardless of dac_valid.

2. When overwrite is enabled, set the intermediary DMA register data_r
 to the RAW value.

  This fixes an issue of the logic analizer that caused the last sample of a DMA
transfer to be visible at the next DMA transfer.

Signed-off-by: dumitruceclan <dumitru.ceclan@analog.com>
 		2024-04-19 19:35:50 +03:00
..
Makefile library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
axi_logic_analyzer.v axi_logic_analyzer: Improve overwrite control logic 2024-04-19 19:35:50 +03:00
axi_logic_analyzer_constr.xdc Add copyright and license to .xdc files 2023-07-25 11:03:02 +03:00
axi_logic_analyzer_ip.tcl Add copyright and license to .tcl, .ttcl files 2023-07-25 15:22:26 +03:00
axi_logic_analyzer_reg.v Replace link in license header from master to main 2024-01-16 16:48:45 +02:00
axi_logic_analyzer_trigger.v Replace link in license header from master to main 2024-01-16 16:48:45 +02:00