37 lines
1.4 KiB
Markdown
37 lines
1.4 KiB
Markdown
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# EVAL-AD463X_FMCZ HDL reference design
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## Building the design
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The design supports almost all the digital interface modes of AD463x, AD403x
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and adaq42xx a new bit stream should be generated each time when the targeted
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configuration changes.
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Default configuration: generic SPI mode for clocking, 2 lanes per channel, SDR
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data capture and capture zone 2.
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### Building attributes
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| Attribute name | Valid values |
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| --------------- | ------------------------------------------------- |
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| CLK_MODE | 0 - SPI / 1 - Echo-clock or Master clock |
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| NUM_OF_SDI | 1 - Interleaved / 2 - 1LPC / 4 - 2LPC / 8 - 4LPC |
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| CAPTURE_ZONE | 1 - negedge of BUSY / 2 - next posedge of CNV |
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| DDR_EN | 0 - MISO runs on SDR / 1 - MISO runs on DDR |
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**Example:**
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make CLK_MODE=0 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=0 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=0 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=0
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make CLK_MODE=1 NUM_OF_SDI=2 CAPTURE_ZONE=2 DDR_EN=1
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make CLK_MODE=1 NUM_OF_SDI=4 CAPTURE_ZONE=2 DDR_EN=1
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make CLK_MODE=1 NUM_OF_SDI=8 CAPTURE_ZONE=2 DDR_EN=1
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## Documentation
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https://wiki.analog.com/resources/eval/user-guides/ad463x/hdl
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