171 lines
6.6 KiB
Tcl
Executable File
171 lines
6.6 KiB
Tcl
Executable File
###############################################################################
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## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# RX parameters for each converter
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set RX_NUM_OF_LANES 16 ; # L
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set RX_NUM_OF_CONVERTERS 1 ; # M
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set RX_SAMPLES_PER_FRAME 16 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL 32 ; # L * 32 / (M * N)
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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set adc_fifo_name axi_ad9213_fifo
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set adc_data_width 512
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set adc_dma_data_width 512
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create_bd_port -dir I glbl_clk_0
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create_bd_port -dir O -from 1 -to 0 hmc7044_csn_o
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create_bd_port -dir I -from 1 -to 0 hmc7044_csn_i
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create_bd_port -dir I hmc7044_clk_i
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create_bd_port -dir O hmc7044_clk_o
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create_bd_port -dir I hmc7044_sdo_i
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create_bd_port -dir O hmc7044_sdo_o
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create_bd_port -dir I hmc7044_sdi_i
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# adc peripherals
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ad_ip_instance util_adxcvr util_adc_xcvr
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ad_ip_parameter util_adc_xcvr CONFIG.CPLL_FBDIV_4_5 5
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ad_ip_parameter util_adc_xcvr CONFIG.TX_NUM_OF_LANES 0
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ad_ip_parameter util_adc_xcvr CONFIG.RX_NUM_OF_LANES 16
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ad_ip_parameter util_adc_xcvr CONFIG.RX_LANE_INVERT 390
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ad_ip_parameter util_adc_xcvr CONFIG.RX_OUT_DIV 1
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ad_ip_instance axi_adxcvr axi_ad9213_xcvr
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ad_ip_parameter axi_ad9213_xcvr CONFIG.ID 0
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ad_ip_parameter axi_ad9213_xcvr CONFIG.NUM_OF_LANES 16
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ad_ip_parameter axi_ad9213_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_ad9213_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_ad9213_xcvr CONFIG.LPM_OR_DFE_N 1
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ad_ip_parameter axi_ad9213_xcvr CONFIG.SYS_CLK_SEL 0x3
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adi_axi_jesd204_rx_create axi_ad9213_jesd 16
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ad_ip_parameter axi_ad9213_jesd/rx CONFIG.SYSREF_IOB false
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ad_ip_parameter axi_ad9213_jesd/rx CONFIG.NUM_INPUT_PIPELINE 2
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adi_tpl_jesd204_rx_create rx_ad9213_tpl_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
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ad_ip_instance axi_dmac axi_ad9213_dma
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ad_ip_parameter axi_ad9213_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad9213_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9213_dma CONFIG.ID 0
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ad_ip_parameter axi_ad9213_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_ad9213_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_ad9213_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad9213_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9213_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9213_dma CONFIG.MAX_BYTES_PER_BURST 4096
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ad_ip_parameter axi_ad9213_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9213_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width
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ad_ip_parameter axi_ad9213_dma CONFIG.DMA_DATA_WIDTH_DEST $adc_dma_data_width
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# reference clocks & resets
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create_bd_port -dir I rx_ref_clk_0
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create_bd_port -dir I rx_ref_clk_1
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ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/qpll_ref_clk_0
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/qpll_ref_clk_4
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/qpll_ref_clk_8
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/qpll_ref_clk_12
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ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_0
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ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_1
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ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_2
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ad_xcvrpll rx_ref_clk_0 util_adc_xcvr/cpll_ref_clk_3
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_4
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_5
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_6
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_7
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_8
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_9
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_10
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_11
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_12
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_13
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_14
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ad_xcvrpll rx_ref_clk_1 util_adc_xcvr/cpll_ref_clk_15
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ad_xcvrpll axi_ad9213_xcvr/up_pll_rst util_adc_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9213_xcvr/up_pll_rst util_adc_xcvr/up_cpll_rst_*
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ad_connect $sys_cpu_resetn util_adc_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_adc_xcvr/up_clk
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# connections (adc)
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ad_xcvrcon util_adc_xcvr axi_ad9213_xcvr axi_ad9213_jesd {4 0 2 1 3 8 9 7 6 11 10 15 12 14 13 5} glbl_clk_0
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## use global clock as device clock instead of rx_out_clk
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delete_bd_objs [get_bd_nets util_adc_xcvr_rx_out_clk_0]
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# connect clocks
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# device clock domain
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ad_connect glbl_clk_0 rx_ad9213_tpl_core/link_clk
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ad_connect glbl_clk_0 axi_ad9213_fifo/adc_clk
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# dma clock domain
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ad_connect $sys_cpu_clk axi_ad9213_fifo/dma_clk
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ad_connect $sys_cpu_clk axi_ad9213_dma/s_axis_aclk
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# connect resets
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ad_connect glbl_clk_0_rstgen/peripheral_reset axi_ad9213_fifo/adc_rst
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ad_connect $sys_cpu_resetn axi_ad9213_dma/m_dest_axi_aresetn
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# connect dataflow
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ad_connect axi_ad9213_jesd/rx_sof rx_ad9213_tpl_core/link_sof
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ad_connect axi_ad9213_jesd/rx_data_tdata rx_ad9213_tpl_core/link_data
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ad_connect axi_ad9213_jesd/rx_data_tvalid rx_ad9213_tpl_core/link_valid
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ad_connect rx_ad9213_tpl_core/adc_valid_0 axi_ad9213_fifo/adc_wr
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ad_connect rx_ad9213_tpl_core/adc_data_0 axi_ad9213_fifo/adc_wdata
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ad_connect rx_ad9213_tpl_core/adc_dovf axi_ad9213_fifo/adc_wovf
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ad_connect axi_ad9213_fifo/dma_wr axi_ad9213_dma/s_axis_valid
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ad_connect axi_ad9213_fifo/dma_wdata axi_ad9213_dma/s_axis_data
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ad_connect axi_ad9213_fifo/dma_wready axi_ad9213_dma/s_axis_ready
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ad_connect axi_ad9213_fifo/dma_xfer_req axi_ad9213_dma/s_axis_xfer_req
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ad_ip_instance axi_quad_spi hmc7044_spi
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ad_ip_parameter hmc7044_spi CONFIG.C_USE_STARTUP 0
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ad_ip_parameter hmc7044_spi CONFIG.C_NUM_SS_BITS 2
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ad_ip_parameter hmc7044_spi CONFIG.C_SCK_RATIO 8
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ad_connect hmc7044_csn_i hmc7044_spi/ss_i
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ad_connect hmc7044_csn_o hmc7044_spi/ss_o
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ad_connect hmc7044_clk_i hmc7044_spi/sck_i
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ad_connect hmc7044_clk_o hmc7044_spi/sck_o
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ad_connect hmc7044_sdo_i hmc7044_spi/io0_i
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ad_connect hmc7044_sdo_o hmc7044_spi/io0_o
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ad_connect hmc7044_sdi_i hmc7044_spi/io1_i
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ad_connect $sys_cpu_clk hmc7044_spi/ext_spi_clk
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# interconnect (cpu)
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ad_cpu_interconnect 0x44a60000 axi_ad9213_xcvr
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ad_cpu_interconnect 0x44a10000 rx_ad9213_tpl_core
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ad_cpu_interconnect 0x44a90000 axi_ad9213_jesd
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ad_cpu_interconnect 0x44a71000 hmc7044_spi
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ad_cpu_interconnect 0x7c420000 axi_ad9213_dma
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# interconnect (gt/adc)
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ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9213_xcvr/m_axi
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ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9213_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-17 mb-7 hmc7044_spi/ip2intc_irpt
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ad_cpu_interrupt ps-12 mb-12 axi_ad9213_dma/irq
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ad_cpu_interrupt ps-11 mb-13 axi_ad9213_jesd/irq
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