42a9da0659
We really only want to apply the CDC constraints if the clocks are actually asynchronous. Unfortunately we can't use if ... inside a xdc script. But we can use expr which has support for a ? b : c if-like expression. We can use that to create helper variables that contains valid clock when the clock domains are asynchronous or {} if they are not. Passing {} as set_false_path/set_max_delay as either the source or destination will cause it to abort and no constraints will be added. Also add -quiet parameters to avoid generating warning if the constraints could not be added. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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README.md
hdl
Analog Devices HDL libraries and projects
Tools version:
- Vivado 2014.4.1
- Quartus 14.0
First time users, it is highly recommended to go through our HDL user guide at the following url:
http://wiki.analog.com/resources/fpga/docs/hdl
For support please visit our FPGA Reference Designs Support Community on EngineerZone: