133 lines
4.3 KiB
Verilog
133 lines
4.3 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsabilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_var_fifo #(
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// parameters
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parameter DATA_WIDTH = 32,
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parameter ADDRESS_WIDTH = 13) (
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input clk,
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input rst,
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input [31:0] depth,
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input [DATA_WIDTH -1:0] data_in,
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input data_in_valid,
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output [DATA_WIDTH-1:0] data_out,
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output data_out_valid,
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output wea_w,
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output en_w,
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output [ADDRESS_WIDTH-1:0] addr_w,
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output [DATA_WIDTH-1:0] din_w,
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output en_r,
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output [ADDRESS_WIDTH-1:0] addr_r,
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input [DATA_WIDTH-1:0] dout_r);
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localparam MAX_DEPTH = (2 ** ADDRESS_WIDTH) - 1;
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// internal registers
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reg [ADDRESS_WIDTH-1:0] addra = 'd0;
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reg [ADDRESS_WIDTH-1:0] addrb = 'd0;
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reg [31:0] depth_d1 = 'd0;
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reg [DATA_WIDTH-1:0] data_in_d1 = 'd0;
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reg [DATA_WIDTH-1:0] data_in_d2 = 'd0;
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reg data_active = 'd0;
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reg fifo_active = 'd0;
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// internal signals
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wire reset;
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wire [DATA_WIDTH-1:0] data_out_s;
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wire data_out_valid_s;
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assign reset = ((rst == 1'b1) || (depth != depth_d1)) ? 1 : 0;
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assign data_out = fifo_active ? data_out_s : data_in_d2;
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assign data_out_valid_s = data_active & data_in_valid;
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assign data_out_valid = fifo_active ? data_out_valid_s : data_in_valid;
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assign wea_w = data_in_valid & fifo_active;
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assign en_w = fifo_active;
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assign addr_w = addra;
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assign din_w = data_in;
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assign en_r = fifo_active;
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assign addr_r = addrb;
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assign data_out_s = dout_r;
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always @(posedge clk) begin
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depth_d1 <= depth;
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if (depth == 32'h0) begin
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fifo_active <= 0;
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end else begin
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fifo_active <= 1;
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end
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if (data_in_valid == 1'b1 && fifo_active == 1'b0) begin
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data_in_d1 <= data_in;
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data_in_d2 <= data_in_d1;
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end
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end
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always @(posedge clk) begin
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if(reset == 1'b1 || fifo_active == 1'b0) begin
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addra <= 0;
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addrb <= 0;
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data_active <= 1'b0;
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end else begin
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if (data_in_valid == 1'b1) begin
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addra <= addra + 1;
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if (data_active == 1'b1) begin
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addrb <= addrb + 1;
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end
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end
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if (addra >= depth || addra > MAX_DEPTH - 2) begin
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data_active <= 1'b1;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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