pluto_hdl_adi/library/jesd204
Lars-Peter Clausen 840dd221b7 jesd204_rx: Count errors only once per character
Typically only one of the character error conditions is true at a time. And
even if multiple errors were present at the same time we'd only want to
count one error per character.

For each character track whether at least one of the monitored error
conditions is true. Then count the number of characters for which at least
one error condition occurred. And finally add that sum to the total numbers
of errors.

This results in a slightly better utilization.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-07-16 09:34:36 +02:00
..
ad_ip_jesd204_tpl_adc jesd204: Update Makefiles 2018-06-11 11:30:47 +03:00
ad_ip_jesd204_tpl_dac jesd204: Update Makefiles 2018-06-11 11:30:47 +03:00
axi_jesd204_common jesd204:up_common: Move cfg_links_disable to 0x086 address space 2018-05-03 19:37:35 +03:00
axi_jesd204_rx jesd204: Add constraints for the rx statistics clock crossing 2018-05-10 16:32:50 +03:00
axi_jesd204_tx jesd204: Fix constraints for axi_jesd_tx 2018-05-10 18:17:32 +03:00
interfaces jesd204: Add RX error statistics (#98) 2018-05-07 15:33:00 +03:00
jesd204_common jesd204: Fix file names 2018-04-11 15:09:54 +03:00
jesd204_rx jesd204_rx: Count errors only once per character 2018-07-16 09:34:36 +02:00
jesd204_rx_static_config jesd204_rx: Add dynamic multi-link support 2018-05-03 18:48:54 +03:00
jesd204_soft_pcs_rx jesd204_soft_pcs_rx: Add support for lane polarity inversion 2018-05-02 09:37:23 +02:00
jesd204_soft_pcs_tx jesd204_soft_pcs_tx: Add support for lane polarity inversion 2018-05-02 09:37:23 +02:00
jesd204_tx jesd204:tx_ctrl: Update the sync_request logic 2018-05-03 19:37:35 +03:00
jesd204_tx_static_config jesd204_tx: Add dynamic multi-link support 2018-05-03 19:37:35 +03:00
scripts jesd204_tx: Add dynamic multi-link support 2018-05-03 19:37:35 +03:00
tb jesd204: Add RX error statistics (#98) 2018-05-07 15:33:00 +03:00
README.md Add ADI JESD204 link layer cores 2017-05-23 11:16:07 +02:00

README.md

Analog Devices JESD204B HDL Support

Licensing

The ADI JESD204 Core is released under the following license, which is different than all other HDL cores in this repository.

Please read this, and understand the freedoms and responsibilities you have by using this source code/core.

The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.

This core is free software, you can use run, copy, study, change, ask questions about and improve this core. Distribution of source, or resulting binaries (including those inside an FPGA or ASIC) require you to release the source of the entire project (excluding the system libraries provide by the tools/compiler/FPGA vendor). These are the terms of the GNU General Public License version 2 as published by the Free Software Foundation.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License version 2 along with this source code, and binary. If not, see http://www.gnu.org/licenses/.

Commercial licenses (with commercial support) of this JESD204 core are also available under terms different than the General Public License. (e.g. they do not require you to accompany any image (FPGA or ASIC) using the JESD204 core with any corresponding source code.) For these alternate terms you must purchase a license from Analog Devices Technology Licensing Office. Users interested in such a license should contact jesd204-licensing@analog.com for more information. This commercial license is sub-licensable (if you purchase chips from Analog Devices, incorporate them into your PCB level product, and purchase a JESD204 license, end users of your product will also have a license to use this core in a commercial setting without releasing their source code).

In addition, we kindly ask you to acknowledge ADI in any program, application or publication in which you use this JESD204 HDL core. (You are not required to do so; it is up to your common sense to decide whether you want to comply with this request or not.) For general publications, we suggest referencing : “The design and implementation of the JESD204 HDL Core used in this project is copyright © 2016-2017, Analog Devices, Inc.”

Support

Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via https://ez.analog.com/community/fpga under the GPL license. If you would like deterministic support when using this core with an ADI component, please investigate a commercial license. Using a non-ADI JESD204 device with this core is possible under the GPL, but Analog Devices will not help with issues you may encounter.

Documenation