20 lines
689 B
Tcl
20 lines
689 B
Tcl
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# instantiate the base design
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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# load all the FIFO related proccesses
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source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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# NOTE: to swap the resources comment the two lines above, and uncomment to two line below
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#source $ad_hdl_dir/projects/common/zc706/zc706_plddr3_dacfifo_bd.tcl
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#source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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# the DAC FIFO has a 500KSMP depth - 1 Mbyte
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set dac_fifo_address_width 15
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# by default PLDDR is used (1 Gbyte), this varible should be ignored
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set adc_fifo_address_width 15
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source ../common/fmcomms11_bd.tcl
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