Go to file
Adrian Costina 43946a54a4 axi_dmac: Added C_FIFO_SIZE parameter 2015-07-24 15:30:10 +03:00
library axi_dmac: Added C_FIFO_SIZE parameter 2015-07-24 15:30:10 +03:00
projects fmcjesdadc1: a5gt, design working with quartus 15.0 2015-07-23 18:11:53 +03:00
.gitattributes Add .gitattributes file 2015-07-01 18:43:51 +02:00
.gitignore gitignore: add non-project stuff 2015-05-01 13:17:14 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md Update README.md 2015-05-20 17:38:08 +03:00

README.md

#HDL Reference Designs

Analog Devices HDL libraries and projects

##NOTE

Beware! This branch is just a realease candidate. Final release expected at end of June.

###Tools version:

###Documentation and support

For first time users, it is highly recommended to go through our HDL user guide.

For support please visit our FPGA Reference Designs Support Community on EngineerZone.