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Adrian Costina 3ea60bca5d fmcjesdadc1: a5gt, design working with quartus 15.0 
- added cpack to the design
- removed 166 MHz clock as it is not needed. DMA destination is 512 bits
- removed clock bridge between DMA and DDR
 		2015-07-23 18:11:53 +03:00
..
a5gt fmcjesdadc1: a5gt, design working with quartus 15.0 2015-07-23 18:11:53 +03:00
a5soc Add .gitattributes file 2015-07-01 18:43:51 +02:00
common Add .gitattributes file 2015-07-01 18:43:51 +02:00
kc705 fmcjesdadc1: Fixed mdc_mdio connection for kc705 2015-06-18 11:04:29 +03:00
vc707 fmcjesdadc1: Fixed vc707 ethernet connections 2015-06-16 15:31:17 +03:00
zc706 Add .gitattributes file 2015-07-01 18:43:51 +02:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00