zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
pluto_hdl_adi/projects/fmcjesdadc1/a5gt
History
Adrian Costina 3ea60bca5d fmcjesdadc1: a5gt, design working with quartus 15.0 
- added cpack to the design
- removed 166 MHz clock as it is not needed. DMA destination is 512 bits
- removed clock bridge between DMA and DDR
 		2015-07-23 18:11:53 +03:00
..
Makefile Makefile: Updated makefiles 2015-06-25 14:59:34 +03:00
system_bd.qsys fmcjesdadc1: a5gt, design working with quartus 15.0 2015-07-23 18:11:53 +03:00
system_constr.sdc fmcjesdadc1: a5gt, design working with quartus 15.0 2015-07-23 18:11:53 +03:00
system_project.tcl a5gt: updates to match a5gt 2014-08-25 10:46:59 -04:00
system_top.v fmcjesdadc1: a5gt, design working with quartus 15.0 2015-07-23 18:11:53 +03:00