219 lines
6.7 KiB
Verilog
219 lines
6.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// this is a sine function (approximate), the basic idea is to approximate sine as a
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// polynomial function (there are a lot of stuff about this on the web)
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`timescale 1ns/100ps
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module ad_dds_sine (
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// sine = sin(angle)
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clk,
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angle,
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sine,
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ddata_in,
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ddata_out);
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// parameters
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parameter DELAY_DATA_WIDTH = 16;
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localparam DW = DELAY_DATA_WIDTH - 1;
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// sine = sin(angle)
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input clk;
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input [ 15:0] angle;
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output [ 15:0] sine;
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input [ DW:0] ddata_in;
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output [ DW:0] ddata_out;
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// internal registers
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reg [ 33:0] s1_data_p = 'd0;
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reg [ 33:0] s1_data_n = 'd0;
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reg [ 15:0] s1_angle = 'd0;
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reg [ DW:0] s1_ddata = 'd0;
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reg [ 18:0] s2_data_0 = 'd0;
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reg [ 18:0] s2_data_1 = 'd0;
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reg [ DW:0] s2_ddata = 'd0;
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reg [ 18:0] s3_data = 'd0;
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reg [ DW:0] s3_ddata = 'd0;
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reg [ 33:0] s4_data2_p = 'd0;
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reg [ 33:0] s4_data2_n = 'd0;
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reg [ 16:0] s4_data1_p = 'd0;
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reg [ 16:0] s4_data1_n = 'd0;
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reg [ DW:0] s4_ddata = 'd0;
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reg [ 16:0] s5_data2_0 = 'd0;
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reg [ 16:0] s5_data2_1 = 'd0;
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reg [ 16:0] s5_data1 = 'd0;
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reg [ DW:0] s5_ddata = 'd0;
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reg [ 16:0] s6_data2 = 'd0;
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reg [ 16:0] s6_data1 = 'd0;
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reg [ DW:0] s6_ddata = 'd0;
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reg [ 33:0] s7_data = 'd0;
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reg [ DW:0] s7_ddata = 'd0;
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reg [ 15:0] sine = 'd0;
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reg [ DW:0] ddata_out = 'd0;
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// internal signals
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wire [ 15:0] angle_s;
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wire [ 33:0] s1_data_s;
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wire [ DW:0] s1_ddata_s;
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wire [ 15:0] s1_angle_s;
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wire [ 33:0] s4_data2_s;
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wire [ DW:0] s4_ddata_s;
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wire [ 16:0] s4_data1_s;
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wire [ 33:0] s7_data2_s;
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wire [ 33:0] s7_data1_s;
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wire [ DW:0] s7_ddata_s;
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// make angle 2's complement
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assign angle_s = {~angle[15], angle[14:0]};
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// level 1 - intermediate
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ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+16)) i_mul_s1 (
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.clk (clk),
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.data_a ({angle_s[15], angle_s}),
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.data_b ({angle_s[15], angle_s}),
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.data_p (s1_data_s),
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.ddata_in ({ddata_in, angle_s}),
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.ddata_out ({s1_ddata_s, s1_angle_s}));
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// 2's complement versions
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always @(posedge clk) begin
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s1_data_p <= s1_data_s;
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s1_data_n <= ~s1_data_s + 1'b1;
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s1_angle <= s1_angle_s;
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s1_ddata <= s1_ddata_s;
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end
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// select partial products
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always @(posedge clk) begin
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s2_data_0 <= (s1_angle[15] == 1'b0) ? s1_data_n[31:13] : s1_data_p[31:13];
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s2_data_1 <= {s1_angle[15], s1_angle[15:0], 2'b00};
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s2_ddata <= s1_ddata;
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end
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// unit-sine
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always @(posedge clk) begin
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s3_data <= s2_data_0 + s2_data_1;
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s3_ddata <= s2_ddata;
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end
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// level 2 - final
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ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH+17)) i_mul_s2 (
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.clk (clk),
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.data_a (s3_data[16:0]),
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.data_b (s3_data[16:0]),
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.data_p (s4_data2_s),
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.ddata_in ({s3_ddata, s3_data[16:0]}),
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.ddata_out ({s4_ddata_s, s4_data1_s}));
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// 2's complement versions
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always @(posedge clk) begin
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s4_data2_p <= s4_data2_s;
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s4_data2_n <= ~s4_data2_s + 1'b1;
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s4_data1_p <= s4_data1_s;
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s4_data1_n <= ~s4_data1_s + 1'b1;
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s4_ddata <= s4_ddata_s;
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end
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// select partial products
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always @(posedge clk) begin
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s5_data2_0 <= (s4_data1_p[16] == 1'b1) ? s4_data2_n[31:15] : s4_data2_p[31:15];
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s5_data2_1 <= s4_data1_n;
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s5_data1 <= s4_data1_p;
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s5_ddata <= s4_ddata;
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end
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// corrected-sine
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always @(posedge clk) begin
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s6_data2 <= s5_data2_0 + s5_data2_1;
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s6_data1 <= s5_data1;
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s6_ddata <= s5_ddata;
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end
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// full-scale
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ad_mul #(.DELAY_DATA_WIDTH(1)) i_mul_s3_2 (
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.clk (clk),
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.data_a (s6_data2),
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.data_b (17'h1d08),
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.data_p (s7_data2_s),
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.ddata_in (1'b0),
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.ddata_out ());
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ad_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_s3_1 (
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.clk (clk),
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.data_a (s6_data1),
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.data_b (17'h7fff),
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.data_p (s7_data1_s),
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.ddata_in (s6_ddata),
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.ddata_out (s7_ddata_s));
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// corrected sum
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always @(posedge clk) begin
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s7_data <= s7_data2_s + s7_data1_s;
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s7_ddata <= s7_ddata_s;
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end
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// output registers
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always @(posedge clk) begin
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sine <= s7_data[30:15];
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ddata_out <= s7_ddata;
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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