186 lines
7.9 KiB
Tcl
186 lines
7.9 KiB
Tcl
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set DEBUG_BUILD 0
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# create board design
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# default ports
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 fixed_io
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create_bd_port -dir O spi0_csn_2_o
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create_bd_port -dir O spi0_csn_1_o
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create_bd_port -dir O spi0_csn_0_o
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create_bd_port -dir I spi0_csn_i
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create_bd_port -dir I spi0_clk_i
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create_bd_port -dir O spi0_clk_o
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create_bd_port -dir I spi0_sdo_i
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create_bd_port -dir O spi0_sdo_o
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create_bd_port -dir I spi0_sdi_i
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create_bd_port -dir I -from 16 -to 0 gpio_i
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create_bd_port -dir O -from 16 -to 0 gpio_o
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create_bd_port -dir O -from 16 -to 0 gpio_t
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# interrupts
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create_bd_port -dir I -type intr ps_intr_00
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create_bd_port -dir I -type intr ps_intr_01
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create_bd_port -dir I -type intr ps_intr_02
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create_bd_port -dir I -type intr ps_intr_03
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create_bd_port -dir I -type intr ps_intr_04
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create_bd_port -dir I -type intr ps_intr_05
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create_bd_port -dir I -type intr ps_intr_06
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create_bd_port -dir I -type intr ps_intr_07
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create_bd_port -dir I -type intr ps_intr_08
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create_bd_port -dir I -type intr ps_intr_09
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create_bd_port -dir I -type intr ps_intr_10
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create_bd_port -dir I -type intr ps_intr_11
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create_bd_port -dir I -type intr ps_intr_12
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create_bd_port -dir I -type intr ps_intr_13
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create_bd_port -dir I -type intr ps_intr_15
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# instance: sys_ps7
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ad_ip_instance processing_system7 sys_ps7
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ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V}
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ad_ip_parameter sys_ps7 CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V}
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ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}
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ad_ip_parameter sys_ps7 CONFIG.PCW_PACKAGE_NAME {clg225}
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ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO {17}
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ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0}
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ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_UART1_IO {MIO 12 .. 13}
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ad_ip_parameter sys_ps7 CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0}
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ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_SD0_PERIPHERAL_ENABLE {0}
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ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_SPI0_SPI0_IO {EMIO}
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ad_ip_parameter sys_ps7 CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}
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ad_ip_parameter sys_ps7 CONFIG.PCW_USE_FABRIC_INTERRUPT {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO}
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ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_IO {MIO 52}
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ad_ip_parameter sys_ps7 CONFIG.PCW_USB0_RESET_ENABLE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_INTR {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_IRQ_F2P_MODE {REVERSE}
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# Clock the whole system of the DDR PLL, disable ARM and IO PLL
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# * PLL: 1000 MHz
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# * DDR: 500 MHz (2.0Gb/s),
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# * CPU: 500 MHz (downclocked to 250 MHz when idle)
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ad_ip_parameter sys_ps7 CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UART_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {DDR PLL}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500}
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ad_ip_parameter sys_ps7 CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {500}
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ad_ip_parameter sys_ps7 CONFIG.PCW_OVERRIDE_BASIC_CLOCK {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5}
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ad_ip_parameter sys_ps7 CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {20}
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ad_ip_parameter sys_ps7 CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {16}
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ad_ip_parameter sys_ps7 CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {6}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {40}
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ad_ip_parameter sys_ps7 CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {40}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {6}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {6}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {5}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {2}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {6}
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ad_ip_parameter sys_ps7 CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {3}
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ad_ip_parameter sys_ps7 CONFIG.PCW_IOPLL_CTRL_FBDIV {30}
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ad_ip_parameter sys_ps7 CONFIG.PCW_ARMPLL_CTRL_FBDIV {30}
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ad_ip_parameter sys_ps7 CONFIG.PCW_DDRPLL_CTRL_FBDIV {30}
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# DDR MT41K256M16 HA-125 (32M, 16bit, 8banks)
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41K256M16 RE-125}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.048}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.050}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.241}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.240}
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ad_ip_parameter sys_ps7 CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {500.0}
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ad_ip_instance axi_iic axi_iic_main
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ad_ip_instance xlconcat sys_concat_intc
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ad_ip_parameter sys_concat_intc CONFIG.NUM_PORTS 16
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ad_ip_instance proc_sys_reset sys_rstgen
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ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
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# system reset/clock definitions
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ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
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ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
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ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
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ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
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ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
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# interface connections
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ad_connect ddr sys_ps7/DDR
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ad_connect gpio_i sys_ps7/GPIO_I
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ad_connect gpio_o sys_ps7/GPIO_O
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ad_connect gpio_t sys_ps7/GPIO_T
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ad_connect fixed_io sys_ps7/FIXED_IO
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ad_connect iic_main axi_iic_main/iic
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# spi connections
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ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
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ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
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ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
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ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
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ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
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ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
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ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
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ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
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ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
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# interrupts
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ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
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ad_connect sys_concat_intc/In15 ps_intr_15
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ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
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ad_connect sys_concat_intc/In13 ps_intr_13
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ad_connect sys_concat_intc/In12 ps_intr_12
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ad_connect sys_concat_intc/In11 ps_intr_11
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ad_connect sys_concat_intc/In10 ps_intr_10
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ad_connect sys_concat_intc/In9 ps_intr_09
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ad_connect sys_concat_intc/In8 ps_intr_08
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ad_connect sys_concat_intc/In7 ps_intr_07
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ad_connect sys_concat_intc/In6 ps_intr_06
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ad_connect sys_concat_intc/In5 ps_intr_05
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ad_connect sys_concat_intc/In4 ps_intr_04
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ad_connect sys_concat_intc/In3 ps_intr_03
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ad_connect sys_concat_intc/In2 ps_intr_02
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ad_connect sys_concat_intc/In1 ps_intr_01
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ad_connect sys_concat_intc/In0 ps_intr_00
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# interconnects
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ad_cpu_interconnect 0x41600000 axi_iic_main
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source ../common/m2k_bd.tcl
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