509 lines
15 KiB
Verilog
Executable File
509 lines
15 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9361 (
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// physical interface (receive)
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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// physical interface (transmit)
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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// transmit master/slave
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dac_enable_in,
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dac_enable_out,
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// delay clock
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delay_clk,
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// dma interface
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l_clk,
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clk,
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adc_dwr,
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adc_ddata,
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adc_dsync,
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adc_dovf,
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adc_dunf,
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dac_drd,
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dac_ddata,
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dac_dovf,
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dac_dunf,
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// axi interface
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s_axi_aclk,
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s_axi_aresetn,
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s_axi_awvalid,
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s_axi_awaddr,
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s_axi_awready,
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s_axi_wvalid,
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s_axi_wdata,
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s_axi_wstrb,
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s_axi_wready,
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s_axi_bvalid,
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s_axi_bresp,
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s_axi_bready,
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s_axi_arvalid,
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s_axi_araddr,
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s_axi_arready,
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s_axi_rvalid,
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s_axi_rdata,
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s_axi_rresp,
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s_axi_rready,
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// monitor signals
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adc_mon_valid,
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adc_mon_data,
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// chipscope signals
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dev_dbg_data,
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dev_l_dbg_data);
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// parameters
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parameter PCORE_ID = 0;
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parameter PCORE_BUFTYPE = 0;
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parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
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parameter PCORE_DAC_DP_DISABLE = 0;
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parameter PCORE_ADC_DP_DISABLE = 0;
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parameter C_S_AXI_MIN_SIZE = 32'hffff;
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parameter C_BASEADDR = 32'hffffffff;
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parameter C_HIGHADDR = 32'h00000000;
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// physical interface (receive)
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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// physical interface (transmit)
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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// master/slave
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input dac_enable_in;
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output dac_enable_out;
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// delay clock
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input delay_clk;
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// dma interface
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output l_clk;
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input clk;
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output adc_dwr;
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output [63:0] adc_ddata;
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output adc_dsync;
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input adc_dovf;
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input adc_dunf;
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output dac_drd;
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input [63:0] dac_ddata;
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input dac_dovf;
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input dac_dunf;
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// axi interface
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input s_axi_aclk;
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input s_axi_aresetn;
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input s_axi_awvalid;
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input [31:0] s_axi_awaddr;
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output s_axi_awready;
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input s_axi_wvalid;
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input [31:0] s_axi_wdata;
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input [ 3:0] s_axi_wstrb;
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output s_axi_wready;
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output s_axi_bvalid;
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output [ 1:0] s_axi_bresp;
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input s_axi_bready;
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input s_axi_arvalid;
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input [31:0] s_axi_araddr;
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output s_axi_arready;
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output s_axi_rvalid;
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output [31:0] s_axi_rdata;
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output [ 1:0] s_axi_rresp;
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input s_axi_rready;
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// monitor interface
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output adc_mon_valid;
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output [47:0] adc_mon_data;
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// chipscope signals
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output [111:0] dev_dbg_data;
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output [ 61:0] dev_l_dbg_data;
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// internal registers
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reg [31:0] up_rdata = 'd0;
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reg up_ack = 'd0;
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// internal clocks and resets
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wire up_clk;
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wire up_rstn;
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wire delay_rst;
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// internal signals
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wire adc_valid_s;
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wire [11:0] adc_data_i1_s;
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wire [11:0] adc_data_q1_s;
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wire [11:0] adc_data_i2_s;
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wire [11:0] adc_data_q2_s;
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wire adc_status_s;
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wire adc_r1_mode_s;
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wire dac_valid_s;
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wire [11:0] dac_data_i1_s;
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wire [11:0] dac_data_q1_s;
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wire [11:0] dac_data_i2_s;
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wire [11:0] dac_data_q2_s;
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wire dac_r1_mode_s;
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wire delay_sel_s;
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wire delay_rwn_s;
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wire [ 7:0] delay_addr_s;
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wire [ 4:0] delay_wdata_s;
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wire [ 4:0] delay_rdata_s;
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wire delay_ack_t_s;
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wire delay_locked_s;
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wire adc_valid_pl_s;
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wire [11:0] adc_data_pl_i1_s;
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wire [11:0] adc_data_pl_q1_s;
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wire [11:0] adc_data_pl_i2_s;
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wire [11:0] adc_data_pl_q2_s;
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wire dac_valid_pl_s;
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wire [11:0] dac_data_pl_i1_s;
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wire [11:0] dac_data_pl_q1_s;
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wire [11:0] dac_data_pl_i2_s;
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wire [11:0] dac_data_pl_q2_s;
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wire dac_lb_enb_i1_s;
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wire dac_pn_enb_i1_s;
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wire dac_lb_enb_q1_s;
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wire dac_pn_enb_q1_s;
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wire dac_lb_enb_i2_s;
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wire dac_pn_enb_i2_s;
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wire dac_lb_enb_q2_s;
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wire dac_pn_enb_q2_s;
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wire adc_lb_enb_i1_s;
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wire adc_pn_oos_i1_s;
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wire adc_pn_err_i1_s;
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wire adc_lb_enb_q1_s;
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wire adc_pn_oos_q1_s;
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wire adc_pn_err_q1_s;
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wire adc_lb_enb_i2_s;
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wire adc_pn_oos_i2_s;
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wire adc_pn_err_i2_s;
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wire adc_lb_enb_q2_s;
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wire adc_pn_oos_q2_s;
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wire adc_pn_err_q2_s;
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wire up_sel_s;
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wire up_wr_s;
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wire [13:0] up_addr_s;
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wire [31:0] up_wdata_s;
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wire [31:0] up_rdata_rx_s;
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wire up_ack_rx_s;
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wire [31:0] up_rdata_tx_s;
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wire up_ack_tx_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rdata <= 'd0;
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up_ack <= 'd0;
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end else begin
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up_rdata <= up_rdata_rx_s | up_rdata_tx_s;
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up_ack <= up_ack_rx_s | up_ack_tx_s;
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end
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end
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// device interface
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axi_ad9361_dev_if #(
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.PCORE_BUFTYPE (PCORE_BUFTYPE),
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.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
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i_dev_if (
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.rx_clk_in_p (rx_clk_in_p),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_data_in_n (rx_data_in_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_data_out_n (tx_data_out_n),
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.l_clk (l_clk),
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.clk (clk),
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.adc_valid (adc_valid_s),
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.adc_data_i1 (adc_data_i1_s),
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.adc_data_q1 (adc_data_q1_s),
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.adc_data_i2 (adc_data_i2_s),
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.adc_data_q2 (adc_data_q2_s),
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.adc_status (adc_status_s),
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.adc_r1_mode (adc_r1_mode_s),
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.dac_valid (dac_valid_s),
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.dac_data_i1 (dac_data_i1_s),
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.dac_data_q1 (dac_data_q1_s),
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.dac_data_i2 (dac_data_i2_s),
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.dac_data_q2 (dac_data_q2_s),
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.dac_r1_mode (dac_r1_mode_s),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_sel (delay_sel_s),
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.delay_rwn (delay_rwn_s),
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.delay_addr (delay_addr_s),
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.delay_wdata (delay_wdata_s),
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.delay_rdata (delay_rdata_s),
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.delay_ack_t (delay_ack_t_s),
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.delay_locked (delay_locked_s),
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.dev_dbg_data (dev_dbg_data),
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.dev_l_dbg_data (dev_l_dbg_data));
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// prbs/loopback interface
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axi_ad9361_pnlb i_pnlb (
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.clk (clk),
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.adc_valid_in (adc_valid_s),
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.adc_data_in_i1 (adc_data_i1_s),
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.adc_data_in_q1 (adc_data_q1_s),
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.adc_data_in_i2 (adc_data_i2_s),
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.adc_data_in_q2 (adc_data_q2_s),
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.dac_valid_in (dac_valid_pl_s),
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.dac_data_in_i1 (dac_data_pl_i1_s),
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.dac_data_in_q1 (dac_data_pl_q1_s),
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.dac_data_in_i2 (dac_data_pl_i2_s),
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.dac_data_in_q2 (dac_data_pl_q2_s),
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.adc_valid (adc_valid_pl_s),
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.adc_data_i1 (adc_data_pl_i1_s),
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.adc_data_q1 (adc_data_pl_q1_s),
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.adc_data_i2 (adc_data_pl_i2_s),
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.adc_data_q2 (adc_data_pl_q2_s),
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.dac_valid (dac_valid_s),
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.dac_data_i1 (dac_data_i1_s),
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.dac_data_q1 (dac_data_q1_s),
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.dac_data_i2 (dac_data_i2_s),
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.dac_data_q2 (dac_data_q2_s),
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.adc_lb_enb_i1 (adc_lb_enb_i1_s),
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.dac_lb_enb_i1 (dac_lb_enb_i1_s),
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.dac_pn_enb_i1 (dac_pn_enb_i1_s),
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.adc_lb_enb_q1 (adc_lb_enb_q1_s),
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.dac_lb_enb_q1 (dac_lb_enb_q1_s),
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.dac_pn_enb_q1 (dac_pn_enb_q1_s),
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.adc_lb_enb_i2 (adc_lb_enb_i2_s),
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.dac_lb_enb_i2 (dac_lb_enb_i2_s),
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.dac_pn_enb_i2 (dac_pn_enb_i2_s),
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.adc_lb_enb_q2 (adc_lb_enb_q2_s),
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.dac_lb_enb_q2 (dac_lb_enb_q2_s),
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.dac_pn_enb_q2 (dac_pn_enb_q2_s),
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.adc_pn_oos_i1 (adc_pn_oos_i1_s),
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.adc_pn_err_i1 (adc_pn_err_i1_s),
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.adc_pn_oos_q1 (adc_pn_oos_q1_s),
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.adc_pn_err_q1 (adc_pn_err_q1_s),
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.adc_pn_oos_i2 (adc_pn_oos_i2_s),
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.adc_pn_err_i2 (adc_pn_err_i2_s),
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.adc_pn_oos_q2 (adc_pn_oos_q2_s),
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.adc_pn_err_q2 (adc_pn_err_q2_s));
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// receive
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axi_ad9361_rx #(
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.PCORE_ID (PCORE_ID),
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.DP_DISABLE (PCORE_ADC_DP_DISABLE))
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i_rx (
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.adc_clk (clk),
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.adc_valid (adc_valid_pl_s),
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.adc_data_i1 (adc_data_pl_i1_s),
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.adc_data_q1 (adc_data_pl_q1_s),
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.adc_data_i2 (adc_data_pl_i2_s),
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.adc_data_q2 (adc_data_pl_q2_s),
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.adc_lb_enb_i1 (adc_lb_enb_i1_s),
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.adc_pn_oos_i1 (adc_pn_oos_i1_s),
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.adc_pn_err_i1 (adc_pn_err_i1_s),
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.adc_lb_enb_q1 (adc_lb_enb_q1_s),
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.adc_pn_oos_q1 (adc_pn_oos_q1_s),
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.adc_pn_err_q1 (adc_pn_err_q1_s),
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.adc_lb_enb_i2 (adc_lb_enb_i2_s),
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.adc_pn_oos_i2 (adc_pn_oos_i2_s),
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.adc_pn_err_i2 (adc_pn_err_i2_s),
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.adc_lb_enb_q2 (adc_lb_enb_q2_s),
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.adc_pn_oos_q2 (adc_pn_oos_q2_s),
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.adc_pn_err_q2 (adc_pn_err_q2_s),
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.adc_status (adc_status_s),
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.adc_r1_mode (adc_r1_mode_s),
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.delay_clk (delay_clk),
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.delay_rst (delay_rst),
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.delay_sel (delay_sel_s),
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.delay_rwn (delay_rwn_s),
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.delay_addr (delay_addr_s),
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.delay_wdata (delay_wdata_s),
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.delay_rdata (delay_rdata_s),
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.delay_ack_t (delay_ack_t_s),
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.delay_locked (delay_locked_s),
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.adc_dwr (adc_dwr),
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.adc_ddata (adc_ddata),
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.adc_dsync (adc_dsync),
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.adc_dovf (adc_dovf),
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.adc_dunf (adc_dunf),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_sel (up_sel_s),
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.up_wr (up_wr_s),
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.up_addr (up_addr_s),
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.up_wdata (up_wdata_s),
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.up_rdata (up_rdata_rx_s),
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.up_ack (up_ack_rx_s),
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.adc_mon_valid (adc_mon_valid),
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.adc_mon_data (adc_mon_data),
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.adc_dbg_trigger (),
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.adc_dbg_data ());
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// transmit
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axi_ad9361_tx #(
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.PCORE_ID (PCORE_ID),
|
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.DP_DISABLE (PCORE_DAC_DP_DISABLE))
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i_tx (
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|
.dac_clk (clk),
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|
.dac_valid (dac_valid_pl_s),
|
|
.dac_lb_enb_i1 (dac_lb_enb_i1_s),
|
|
.dac_pn_enb_i1 (dac_pn_enb_i1_s),
|
|
.dac_data_i1 (dac_data_pl_i1_s),
|
|
.dac_lb_enb_q1 (dac_lb_enb_q1_s),
|
|
.dac_pn_enb_q1 (dac_pn_enb_q1_s),
|
|
.dac_data_q1 (dac_data_pl_q1_s),
|
|
.dac_lb_enb_i2 (dac_lb_enb_i2_s),
|
|
.dac_pn_enb_i2 (dac_pn_enb_i2_s),
|
|
.dac_data_i2 (dac_data_pl_i2_s),
|
|
.dac_lb_enb_q2 (dac_lb_enb_q2_s),
|
|
.dac_pn_enb_q2 (dac_pn_enb_q2_s),
|
|
.dac_data_q2 (dac_data_pl_q2_s),
|
|
.dac_r1_mode (dac_r1_mode_s),
|
|
.dac_enable_in (dac_enable_in),
|
|
.dac_enable_out (dac_enable_out),
|
|
.dac_drd (dac_drd),
|
|
.dac_ddata (dac_ddata),
|
|
.dac_dovf (dac_dovf),
|
|
.dac_dunf (dac_dunf),
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_sel (up_sel_s),
|
|
.up_wr (up_wr_s),
|
|
.up_addr (up_addr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_rdata (up_rdata_tx_s),
|
|
.up_ack (up_ack_tx_s));
|
|
|
|
// axi interface
|
|
|
|
up_axi #(
|
|
.PCORE_BASEADDR (C_BASEADDR),
|
|
.PCORE_HIGHADDR (C_HIGHADDR))
|
|
i_up_axi (
|
|
.up_rstn (up_rstn),
|
|
.up_clk (up_clk),
|
|
.up_axi_awvalid (s_axi_awvalid),
|
|
.up_axi_awaddr (s_axi_awaddr),
|
|
.up_axi_awready (s_axi_awready),
|
|
.up_axi_wvalid (s_axi_wvalid),
|
|
.up_axi_wdata (s_axi_wdata),
|
|
.up_axi_wstrb (s_axi_wstrb),
|
|
.up_axi_wready (s_axi_wready),
|
|
.up_axi_bvalid (s_axi_bvalid),
|
|
.up_axi_bresp (s_axi_bresp),
|
|
.up_axi_bready (s_axi_bready),
|
|
.up_axi_arvalid (s_axi_arvalid),
|
|
.up_axi_araddr (s_axi_araddr),
|
|
.up_axi_arready (s_axi_arready),
|
|
.up_axi_rvalid (s_axi_rvalid),
|
|
.up_axi_rresp (s_axi_rresp),
|
|
.up_axi_rdata (s_axi_rdata),
|
|
.up_axi_rready (s_axi_rready),
|
|
.up_sel (up_sel_s),
|
|
.up_wr (up_wr_s),
|
|
.up_addr (up_addr_s),
|
|
.up_wdata (up_wdata_s),
|
|
.up_rdata (up_rdata),
|
|
.up_ack (up_ack));
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|