186 lines
6.6 KiB
Verilog
Executable File
186 lines
6.6 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// PN monitors
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`timescale 1ns/100ps
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module axi_ad9361_rx_pnmon (
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// adc interface
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adc_clk,
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adc_valid,
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adc_data_i,
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adc_data_q,
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// pn out of sync and error
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adc_pn_oos,
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adc_pn_err);
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// adc interface
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input adc_clk;
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input adc_valid;
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input [11:0] adc_data_i;
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input [11:0] adc_data_q;
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// pn out of sync and error
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output adc_pn_oos;
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output adc_pn_err;
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// internal registers
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reg [15:0] adc_data = 'd0;
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reg [15:0] adc_pn_data = 'd0;
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reg adc_valid_d = 'd0;
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reg adc_iq_match = 'd0;
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reg adc_pn_match_d = 'd0;
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reg adc_pn_match_z = 'd0;
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reg adc_pn_err = 'd0;
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reg [ 6:0] adc_pn_oos_count = 'd0;
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reg adc_pn_oos = 'd0;
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// internal signals
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wire [11:0] adc_data_i_s;
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wire [11:0] adc_data_q_s;
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wire [11:0] adc_data_q_rev_s;
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wire [15:0] adc_data_s;
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wire adc_iq_match_s;
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wire [15:0] adc_pn_data_s;
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wire adc_pn_match_d_s;
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wire adc_pn_match_z_s;
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wire adc_pn_match_s;
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wire adc_pn_update_s;
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wire adc_pn_err_s;
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// prbs function
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function [15:0] pnfn;
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input [15:0] din;
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reg [15:0] dout;
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begin
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dout = {din[14:0], ~((^din[15:4]) ^ (^din[2:1]))};
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pnfn = dout;
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end
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endfunction
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// bit reversal function
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function [11:0] brfn;
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input [11:0] din;
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reg [11:0] dout;
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begin
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dout[11] = din[ 0];
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dout[10] = din[ 1];
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dout[ 9] = din[ 2];
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dout[ 8] = din[ 3];
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dout[ 7] = din[ 4];
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dout[ 6] = din[ 5];
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dout[ 5] = din[ 6];
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dout[ 4] = din[ 7];
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dout[ 3] = din[ 8];
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dout[ 2] = din[ 9];
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dout[ 1] = din[10];
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dout[ 0] = din[11];
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brfn = dout;
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end
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endfunction
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// assuming lower nibble is lost-
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assign adc_data_i_s = ~adc_data_i;
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assign adc_data_q_s = ~adc_data_q;
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assign adc_data_q_rev_s = brfn(adc_data_q_s);
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assign adc_data_s = {adc_data_i_s, adc_data_q_rev_s[3:0]};
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assign adc_iq_match_s = (adc_data_i_s[7:0] == adc_data_q_rev_s[11:4]) ? 1'b1 : 1'b0;
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// pn sequence checking algorithm is commonly used in most applications.
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// if oos is asserted (pn is out of sync):
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// next sequence is generated from the incoming data.
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// if 64 sequences match consecutively, oos is cleared (de-asserted).
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// if oos is de-asserted (pn is in sync)
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// next sequence is generated from the current sequence.
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// if 64 sequences mismatch consecutively, oos is set (asserted).
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// if oos is de-asserted, any spurious mismatches sets the error register.
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// ideally, processor should make sure both oos == 0x0 and err == 0x0.
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assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_data_s : adc_pn_data;
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assign adc_pn_match_d_s = (adc_data_s == adc_pn_data) ? 1'b1 : 1'b0;
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assign adc_pn_match_z_s = (adc_data_s == adc_data) ? 1'b0 : 1'b1;
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assign adc_pn_match_s = adc_iq_match & adc_pn_match_d & adc_pn_match_z;
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assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
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assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
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// pn oos and counters (64 to clear and set).
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always @(posedge adc_clk) begin
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if (adc_valid == 1'b1) begin
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adc_data <= adc_data_s;
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adc_pn_data <= pnfn(adc_pn_data_s);
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end
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adc_valid_d <= adc_valid;
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adc_iq_match <= adc_iq_match_s;
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adc_pn_match_d <= adc_pn_match_d_s;
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adc_pn_match_z <= adc_pn_match_z_s;
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if (adc_valid_d == 1'b1) begin
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adc_pn_err <= adc_pn_err_s;
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if (adc_pn_update_s == 1'b1) begin
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if (adc_pn_oos_count >= 16) begin
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adc_pn_oos_count <= 'd0;
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adc_pn_oos <= ~adc_pn_oos;
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end else begin
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adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
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adc_pn_oos <= adc_pn_oos;
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end
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end else begin
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adc_pn_oos_count <= 'd0;
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adc_pn_oos <= adc_pn_oos;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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