404 lines
12 KiB
Verilog
404 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR
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// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT,
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// This is the LVDS/DDR interface
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`timescale 1ns/100ps
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module axi_ad9467_if (
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// adc interface (clk, data, over-range)
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adc_clk_in_p,
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adc_clk_in_n,
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adc_data_in_p,
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adc_data_in_n,
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adc_data_or_p,
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adc_data_or_n,
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// interface outputs
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adc_clk,
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adc_data,
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adc_or,
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adc_ddr_edgesel,
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// delay control signals
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delay_sel,
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delay_rwn,
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delay_addr,
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delay_wdata,
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delay_clk,
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delay_ack,
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delay_rst,
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delay_rdata,
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delay_locked);
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// This parameter controls the buffer type based on the target device.
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parameter PCORE_BUFTYPE = 0;
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parameter C_DEVICE_7SERIES = 0;
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parameter C_DEVICE_VIRTEX6 = 1;
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parameter PCORE_IODELAY_GROUP = "dev_if_delay_group";
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// adc interface (clk, data, over-range)
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input adc_clk_in_p;
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input adc_clk_in_n;
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input [ 7:0] adc_data_in_p;
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input [ 7:0] adc_data_in_n;
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input adc_data_or_p;
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input adc_data_or_n;
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// interface outputs
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output adc_clk;
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output [15:0] adc_data;
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output adc_or;
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input adc_ddr_edgesel;
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// delay control signals
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input delay_sel;
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input delay_rwn;
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input [ 7:0] delay_addr;
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input [ 4:0] delay_wdata;
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input delay_clk;
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input delay_rst;
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output delay_ack;
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output [ 4:0] delay_rdata;
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output delay_locked;
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reg [ 7:0] adc_data_p = 'd0;
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reg [ 7:0] adc_data_n = 'd0;
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reg [ 7:0] adc_data_n_d = 'd0;
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reg [ 7:0] adc_dmux_a = 'd0;
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reg [ 7:0] adc_dmux_b = 'd0;
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reg [15:0] adc_data = 'd0;
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reg adc_or_p = 'd0;
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reg adc_or_n = 'd0;
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reg adc_or = 'd0;
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reg [ 8:0] delay_ld = 'd0;
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reg delay_ack = 'd0;
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reg [ 4:0] delay_rdata = 'd0;
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wire [ 4:0] delay_rdata_s[8:0];
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wire [ 7:0] adc_data_ibuf_s;
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wire [ 7:0] adc_data_idelay_s;
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wire [ 7:0] adc_data_p_s;
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wire [ 7:0] adc_data_n_s;
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wire adc_or_ibuf_s;
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wire adc_or_idelay_s;
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wire adc_or_p_s;
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wire adc_or_n_s;
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wire adc_clk_ibuf_s;
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genvar l_inst;
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// The adc data is 8bits ddr, and here it is demuxed to 16bits.
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// The samples may be selected to be either positive first,
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// or negative first.
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always @(posedge adc_clk) begin
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adc_data_p <= adc_data_p_s;
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adc_data_n <= adc_data_n_s;
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adc_data_n_d <= adc_data_n;
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adc_dmux_a <= (adc_ddr_edgesel == 1'b1) ? adc_data_n : adc_data_p;
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adc_dmux_b <= (adc_ddr_edgesel == 1'b1) ? adc_data_p : adc_data_n_d;
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adc_data[15] <= adc_dmux_b[7];
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adc_data[14] <= adc_dmux_a[7];
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adc_data[13] <= adc_dmux_b[6];
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adc_data[12] <= adc_dmux_a[6];
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adc_data[11] <= adc_dmux_b[5];
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adc_data[10] <= adc_dmux_a[5];
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adc_data[ 9] <= adc_dmux_b[4];
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adc_data[ 8] <= adc_dmux_a[4];
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adc_data[ 7] <= adc_dmux_b[3];
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adc_data[ 6] <= adc_dmux_a[3];
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adc_data[ 5] <= adc_dmux_b[2];
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adc_data[ 4] <= adc_dmux_a[2];
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adc_data[ 3] <= adc_dmux_b[1];
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adc_data[ 2] <= adc_dmux_a[1];
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adc_data[ 1] <= adc_dmux_b[0];
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adc_data[ 0] <= adc_dmux_a[0];
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adc_or_p <= adc_or_p_s;
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adc_or_n <= adc_or_n_s;
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if ((adc_or_p == 1'b1) || (adc_or_n == 1'b1)) begin
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adc_or <= 1'b1;
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end else begin
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adc_or <= 1'b0;
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end
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end
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// The delay write interface, each delay element can be individually
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// addressed, and a delay value can be directly loaded (no INC/DEC stuff)
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always @(posedge delay_clk) begin
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if ((delay_sel == 1'b1) && (delay_rwn == 1'b0)) begin
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case (delay_addr)
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8'd8 : delay_ld <= 9'h100;
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8'd7 : delay_ld <= 9'h080;
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8'd6 : delay_ld <= 9'h040;
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8'd5 : delay_ld <= 9'h020;
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8'd4 : delay_ld <= 9'h010;
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8'd3 : delay_ld <= 9'h008;
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8'd2 : delay_ld <= 9'h004;
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8'd1 : delay_ld <= 9'h002;
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8'd0 : delay_ld <= 9'h001;
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default: delay_ld <= 9'h000;
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endcase
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end else begin
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delay_ld <= 9'h000;
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end
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end
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// delay read interface, a delay ack toggle is used to transfer data to the
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// processor side- delay locked is independently transferred
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always @(posedge delay_clk) begin
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case (delay_addr)
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8'd8 : delay_rdata <= delay_rdata_s[8];
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8'd7 : delay_rdata <= delay_rdata_s[7];
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8'd6 : delay_rdata <= delay_rdata_s[6];
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8'd5 : delay_rdata <= delay_rdata_s[5];
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8'd4 : delay_rdata <= delay_rdata_s[4];
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8'd3 : delay_rdata <= delay_rdata_s[3];
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8'd2 : delay_rdata <= delay_rdata_s[2];
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8'd1 : delay_rdata <= delay_rdata_s[1];
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8'd0 : delay_rdata <= delay_rdata_s[0];
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default: delay_rdata <= 5'd0;
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endcase
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if (delay_sel == 1'b1) begin
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delay_ack <= ~delay_ack;
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end
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end
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// The data interface, data signals goes through a LVDS input buffer, then
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// a delay element (1/32th of a 200MHz clock) and finally an input DDR demux.
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generate
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for (l_inst = 0; l_inst <= 7; l_inst = l_inst + 1) begin : g_adc_if
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IBUFDS i_data_ibuf (
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.I (adc_data_in_p[l_inst]),
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.IB (adc_data_in_n[l_inst]),
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.O (adc_data_ibuf_s[l_inst]));
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if (PCORE_BUFTYPE == C_DEVICE_VIRTEX6) begin
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(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
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IODELAYE1 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("I"),
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.HIGH_PERFORMANCE_MODE ("TRUE"),
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.IDELAY_TYPE ("VAR_LOADABLE"),
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.IDELAY_VALUE (0),
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.ODELAY_TYPE ("FIXED"),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.SIGNAL_PATTERN ("DATA"))
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i_data_idelay (
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.T (1'b1),
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.CE (1'b0),
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.INC (1'b0),
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.CLKIN (1'b0),
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.DATAIN (1'b0),
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.ODATAIN (1'b0),
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.CINVCTRL (1'b0),
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.C (delay_clk),
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.IDATAIN (adc_data_ibuf_s[l_inst]),
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.DATAOUT (adc_data_idelay_s[l_inst]),
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.RST (delay_ld[l_inst]),
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.CNTVALUEIN (delay_wdata),
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.CNTVALUEOUT (delay_rdata_s[l_inst]));
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end else begin
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(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE ("VAR_LOAD"),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA"))
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i_data_idelay (
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.CE (1'b0),
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.INC (1'b0),
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.DATAIN (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (delay_clk),
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.IDATAIN (adc_data_ibuf_s[l_inst]),
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.DATAOUT (adc_data_idelay_s[l_inst]),
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.LD (delay_ld[l_inst]),
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.CNTVALUEIN (delay_wdata),
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.CNTVALUEOUT (delay_rdata_s[l_inst]));
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end
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IDDR #(
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
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.SRTYPE ("ASYNC"))
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i_data_ddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (adc_clk),
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.D (adc_data_idelay_s[l_inst]),
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.Q1 (adc_data_p_s[l_inst]),
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.Q2 (adc_data_n_s[l_inst]));
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end
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endgenerate
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// The over-range interface, it follows a similar path as the data signals.
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IBUFDS i_or_ibuf (
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.I (adc_data_or_p),
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.IB (adc_data_or_n),
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.O (adc_or_ibuf_s));
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generate
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if (PCORE_BUFTYPE == C_DEVICE_VIRTEX6) begin
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(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
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IODELAYE1 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("I"),
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.HIGH_PERFORMANCE_MODE ("TRUE"),
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.IDELAY_TYPE ("VAR_LOADABLE"),
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.IDELAY_VALUE (0),
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.ODELAY_TYPE ("FIXED"),
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.ODELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.SIGNAL_PATTERN ("DATA"))
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i_or_idelay (
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.T (1'b1),
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.CE (1'b0),
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.INC (1'b0),
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.CLKIN (1'b0),
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.DATAIN (1'b0),
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.ODATAIN (1'b0),
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.CINVCTRL (1'b0),
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.C (delay_clk),
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.IDATAIN (adc_or_ibuf_s),
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.DATAOUT (adc_or_idelay_s),
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.RST (delay_ld[8]),
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.CNTVALUEIN (delay_wdata),
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.CNTVALUEOUT (delay_rdata_s[8]));
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end else begin
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(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
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IDELAYE2 #(
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.CINVCTRL_SEL ("FALSE"),
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.DELAY_SRC ("IDATAIN"),
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.HIGH_PERFORMANCE_MODE ("FALSE"),
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.IDELAY_TYPE ("VAR_LOAD"),
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.IDELAY_VALUE (0),
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.REFCLK_FREQUENCY (200.0),
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.PIPE_SEL ("FALSE"),
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.SIGNAL_PATTERN ("DATA"))
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i_or_idelay (
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.CE (1'b0),
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.INC (1'b0),
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.DATAIN (1'b0),
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.LDPIPEEN (1'b0),
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.CINVCTRL (1'b0),
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.REGRST (1'b0),
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.C (delay_clk),
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.IDATAIN (adc_or_ibuf_s),
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.DATAOUT (adc_or_idelay_s),
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.LD (delay_ld[8]),
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.CNTVALUEIN (delay_wdata),
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.CNTVALUEOUT (delay_rdata_s[8]));
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end
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endgenerate
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IDDR #(
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.INIT_Q1 (1'b0),
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.INIT_Q2 (1'b0),
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.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"),
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.SRTYPE ("ASYNC"))
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i_or_ddr (
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.CE (1'b1),
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.R (1'b0),
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.S (1'b0),
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.C (adc_clk),
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.D (adc_or_idelay_s),
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.Q1 (adc_or_p_s),
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.Q2 (adc_or_n_s));
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// The clock path is a simple clock buffer after a LVDS input buffer.
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// It is possible for this logic to be replaced with a OSERDES based data capture.
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// The reason for such a simple interface here is because this reference design
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// is used for various boards (native fmc and/or evaluation boards). The pinouts
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// of the FPGA - ADC interface is probably do not allow a OSERDES placement.
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IBUFGDS i_clk_ibuf (
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.I (adc_clk_in_p),
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.IB (adc_clk_in_n),
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.O (adc_clk_ibuf_s));
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generate
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if (PCORE_BUFTYPE == C_DEVICE_VIRTEX6) begin
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BUFR #(.BUFR_DIVIDE ("BYPASS")) i_clk_gbuf (
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.CLR (1'b0),
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.CE (1'b1),
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.I (adc_clk_ibuf_s),
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.O (adc_clk));
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end else begin
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BUFG i_clk_gbuf (
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.I (adc_clk_ibuf_s),
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.O (adc_clk));
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end
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endgenerate
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// The delay controller. Refer to Xilinx doc. for details.
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// The GROUP directive controls which delay elements this is associated with.
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(* IODELAY_GROUP = PCORE_IODELAY_GROUP *)
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IDELAYCTRL i_delay_ctrl (
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.RST (delay_rst),
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.REFCLK (delay_clk),
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.RDY (delay_locked));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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