148 lines
5.0 KiB
Verilog
148 lines
5.0 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_rfifo (
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rstn,
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m_clk,
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m_rd,
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m_rdata,
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m_runf,
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s_clk,
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s_rd,
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s_rdata,
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s_runf,
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fifo_rst,
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fifo_wr,
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fifo_wdata,
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fifo_wfull,
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fifo_rd,
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fifo_rdata,
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fifo_rempty,
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fifo_runf);
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// parameters (S) bus width must be greater than (M)
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parameter M_DATA_WIDTH = 32;
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parameter S_DATA_WIDTH = 64;
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// common clock
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input rstn;
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// master/slave write
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input m_clk;
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input m_rd;
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output [M_DATA_WIDTH-1:0] m_rdata;
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output m_runf;
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input s_clk;
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output s_rd;
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input [S_DATA_WIDTH-1:0] s_rdata;
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input s_runf;
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// fifo interface
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output fifo_rst;
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output fifo_wr;
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output [S_DATA_WIDTH-1:0] fifo_wdata;
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input fifo_wfull;
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output fifo_rd;
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input [M_DATA_WIDTH-1:0] fifo_rdata;
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input fifo_rempty;
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input fifo_runf;
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// internal registers
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reg s_rd = 'd0;
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reg fifo_wr = 'd0;
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reg m_runf_m1 = 'd0;
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reg m_runf_m2 = 'd0;
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reg m_runf = 'd0;
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// internal signals
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wire m_runf_s;
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// defaults
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assign fifo_rst = ~rstn;
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// independent clocks and buswidths- simply expect
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// user to set a reasonable threshold on the full signal
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always @(posedge s_clk) begin
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s_rd <= ~fifo_wfull;
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fifo_wr <= ~fifo_wfull;
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end
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genvar s;
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generate
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for (s = 0; s < S_DATA_WIDTH; s = s + 1) begin: g_wdata
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assign fifo_wdata[s] = s_rdata[(S_DATA_WIDTH-1)-s];
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end
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endgenerate
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// read is non-destructive
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assign fifo_rd = m_rd;
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assign m_runf_s = s_runf | fifo_runf | fifo_rempty;
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always @(posedge m_clk) begin
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m_runf_m1 <= m_runf_s;
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m_runf_m2 <= m_runf_m1;
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m_runf <= m_runf_m2;
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end
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genvar m;
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generate
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for (m = 0; m < M_DATA_WIDTH; m = m + 1) begin: g_rdata
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assign m_rdata[m] = fifo_rdata[(M_DATA_WIDTH-1)-m];
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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