Laszlo Nagy 454b900f90 jesd204: Xilinx: NP=12 support ... To support deterministic latency with non-power of two octets per frame (F=3,6) the interface width towards the transport layer must be resized to match integer multiple of frames. e.g Input datapath width = 4; Output datpath width = 6; for F=3 one beat contains 2 frames for F=6 one beat contains 1 frame The width change is realized with a gearbox. Due the interface width change the single clock domain core is split in two clock domains. - Link clock : lane rate / 40 for input datapath width of 4 octets 8b10b - lane rate / 20 for input datapath width of 8 octets 8b10b - lane rate / 66 for input datapath width of 8 octets 64b66b - Device clock : Link clock * input data path width / output datapath width Interface to transport layer and SYSREF handling is moved to device clock domain. The configuration interface reflects the dual clock domain. If Input and Output datapath width matches, the gearbox is no longer required, a single clock can be connected to both clocks.		2021-02-05 15:24:15 +02:00
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Makefile	library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl	2019-06-29 06:53:51 +03:00
interfaces_ip.tcl	jesd204: Xilinx: NP=12 support	2021-02-05 15:24:15 +02:00