Jorge Marques 55d4215f45 README.md: header, docs info; docs: license, fixes ... Add documentation info to the README.md At adi_hdl_parser.py, filter "_signal_clock" and "_signal_reset" pseudo buses from component.xml files, append them as description in the ports table, in the format "{Bus} [...] is synchronous to this {domain}". Also, adds collapsible directive Signed-off-by: Jorge Marques <jorge.marques@analog.com>		2023-09-27 14:36:34 -03:00
..
tutorial	docs: Include sphinx documentation	2023-09-27 14:36:34 -03:00
axi_spi_engine.rst	README.md: header, docs info; docs: license, fixes	2023-09-27 14:36:34 -03:00
control-interface.rst	docs: Include sphinx documentation	2023-09-27 14:36:34 -03:00
index.rst	docs: update link roles, .gitignore	2023-09-27 14:36:34 -03:00
instruction-format.rst	docs: Include sphinx documentation	2023-09-27 14:36:34 -03:00
offload-control-interface.rst	docs: Include sphinx documentation	2023-09-27 14:36:34 -03:00
spi-bus-interface.rst	docs: review fixes	2023-09-27 14:36:34 -03:00
spi_bus.svg	docs: Include sphinx documentation	2023-09-27 14:36:34 -03:00
spi_engine.svg	docs: Include sphinx documentation	2023-09-27 14:36:34 -03:00
spi_engine_execution.rst	docs: automate parameters and interfaces tables	2023-09-27 14:36:34 -03:00
spi_engine_interconnect.rst	docs: automate parameters and interfaces tables	2023-09-27 14:36:34 -03:00
spi_engine_offload.rst	docs: review fixes	2023-09-27 14:36:34 -03:00
tutorial.rst	docs: update link roles, .gitignore	2023-09-27 14:36:34 -03:00