253 lines
7.8 KiB
ReStructuredText
253 lines
7.8 KiB
ReStructuredText
.. _spi_engine instruction-format:
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SPI Engine Instruction Set Specification
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================================================================================
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The SPI Engine instruction set is a simple 16-bit instruction set of which
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12-bit is currently allocated (bits 15,14,11,10 are always 0).
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Instructions
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Transfer Instruction
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--------------------------------------------------------------------------------
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== == == == == == = = = = = = = = = =
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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== == == == == == = = = = = = = = = =
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0 0 0 0 0 0 r w n n n n n n n n
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== == == == == == = = = = = = = = = =
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The transfer instructions perform a low-level SPI transfer. It will generate
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SCLK transitions for the specified amount of cycles according to the SPI
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configuration register. If the r bit is set the SDI pin will be sampled and
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stored in the shift register at the end of each word the data is output on the
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SDI_DATA stream. If the w bit is set the SDO pin will be updated with the data
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received from the SDO_DATA stream. If the w bit is set the sdo_t signal will
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also be set to 0 for the duration of the transfer. If the SDI_DATA stream is not
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able to accept data or the SDO_DATA stream is not able to provide data the
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execution is stalled at the end/start of the transfer until data is
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accepted/becomes available.
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.. list-table::
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:widths: 10 15 75
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:header-rows: 1
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* - Bits
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- Name
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- Description
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* - r
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- Read
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- If set to 1 data will be read from the SDI pin during and the read words
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will be available on the SDI_DATA interface.
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* - w
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- Write
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- If set to 1 data will be taken from the SDO_DATA interface and output on
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the SDO pin.
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* - n
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- Length
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- n + 1 number of words that will be transferred.
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Chip-select Instruction
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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== == == == == == = = = = = = = = = =
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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== == == == == == = = = = = = = = = =
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0 0 0 1 0 0 t t s s s s s s s s
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== == == == == == = = = = = = = = = =
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The chip-select instruction updates the value chip-select output signal of the
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SPI Engine execution module.
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Before and after the update is performed the execution module is paused for the
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specified delay. The length of the delay depends on the module clock frequency,
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the setting of the prescaler register and the t parameter of the instruction.
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This delay is inserted before and after the update of the chip-select signal,
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so the total execution time of the chip-select
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instruction is twice the delay.
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.. math::
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delay = t * \frac{div + 1}{f_{clk}}
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.. list-table::
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:widths: 10 15 75
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:header-rows: 1
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* - Bits
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- Name
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- Description
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* - t
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- Delay
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- Delay before and after setting the new configuration.
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* - s
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- Chip-select
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- The new chip-select configuration.
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Configuration Write Instruction
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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== == == == == == = = = = = = = = = =
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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== == == == == == = = = = = = = = = =
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0 0 1 0 0 0 r r v v v v v v v v
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== == == == == == = = = = = = = = = =
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The configuration writes instruction updates a
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:ref:`spi_engine configutarion-registers`
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of the SPI Engine execution module with a new value.
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.. list-table::
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:widths: 10 15 75
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:header-rows: 1
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* - Bits
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- Name
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- Description
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* - r
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- Register
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- Configuration register address.
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2'b00 = :ref:`spi_engine prescaler-configuration-register`
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2'b01 = :ref:`spi_engine spi-configuration-register`
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2'b10 = :ref:`spi_engine dynamic-transfer-length-register`.
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* - v
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- Value
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- New value for the configuration register.
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Synchronize Instruction
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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== == == == == == = = = = = = = = = =
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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== == == == == == = = = = = = = = = =
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0 0 1 1 0 0 0 0 n n n n n n n n
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== == == == == == = = = = = = = = = =
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The synchronize instruction generates a synchronization event on the SYNC output
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stream. This can be used to monitor the progress of the command stream. The
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synchronize instruction is also used by the :ref:`spi_engine interconnect`
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module to identify the end of a transaction and re-start the arbitration process.
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.. list-table::
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:widths: 10 15 75
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:header-rows: 1
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* - Bits
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- Name
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- Description
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* - n
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- id
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- Value of the generated synchronization event.
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Sleep Instruction
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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== == == == == == = = = = = = = = = =
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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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== == == == == == = = = = = = = = = =
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0 0 1 1 0 0 0 1 t t t t t t t t
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== == == == == == = = = = = = = = = =
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The sleep instruction stops the execution of the command stream for the
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specified amount of time. The time is based on the external clock frequency the
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configuration value of the prescaler register and the time parameter of the
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instruction.
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.. math::
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sleep\_time = \frac{(t + 1) * ((div + 1) * 2)}{f_{clk}}
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.. list-table::
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:widths: 10 15 75
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:header-rows: 1
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* - Bits
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- Name
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- Description
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* - t
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- Time
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- The amount of time to wait.
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.. _spi_engine configutarion-registers:
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Configuration Registers
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--------------------------------------------------------------------------------
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The SPI Engine execution module has a set of 8-bit configuration registers which
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can be used to dynamically modify the behavior of the module at runtime.
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.. _spi_engine spi-configuration-register:
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SPI Configuration Register
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The SPI configuration register configures various aspects of the low-level SPI
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bus behavior.
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.. list-table::
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:widths: 10 15 75
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:header-rows: 1
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* - Bits
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- Name
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- Description
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* - [7:3]
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- reserved
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- Must always be 0.
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* - [2]
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- three_wire
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- Configures the output of the three_wire pin.
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* - [1]
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- CPOL
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- Configures the polarity of the SCLK signal. When 0, the idle state of
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the SCLK signal is low. When 1, the idle state of the SCLK signal is
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high.
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* - [0]
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- CPHA
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- Configures the phase of the SCLK signal. When 0, data is updated on the
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leading edge and sampled on the trailing edge. When 1, data is is
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sampled on the leading edge and updated on the trailing edge.
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.. _spi_engine prescaler-configuration-register:
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Prescaler Configuration Register
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The prescaler configuration register configures the divider that is applied to
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the module clock when generating the SCLK signal and other internal control
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signals used by the sleep and chip-select commands.
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===== ==== =======================
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Bits Name Description
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===== ==== =======================
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[7:0] div Prescaler clock divider
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===== ==== =======================
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The frequency of the SCLK signal is derived from the module clock frequency
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using the following formula:
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.. math::
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f_{sclk} = \frac{f_{clk}}{((div + 1) * 2)}
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If no prescaler block is present div is 0.
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.. _spi_engine dynamic-transfer-length-register:
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Dynamic Transfer Length Register
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The dynamic transfer length register sets the length (in bits) of a transfer. By
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default, the transfer length is equal to the DATA_WIDTH of the execution module.
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If required the user can reduce this length by setting this register. A general
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rule of thumb is to set the DATA_WIDTH parameter to the largest transfer length
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supported by the target device.
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===== ==== =======================
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Bits Name Description
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===== ==== =======================
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[7:0] div Dynamic transfer length
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===== ==== =======================
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