Lars-Peter Clausen 45f87b46c2 ad_lvds_in: Use "SAME_EDGE" mode ... Currently the IDDRs are configured in SAME_EDGE_PIPELINED mode, but then the negative data is delayed by an additional clock cycle. This is the same behaviour as using the IDDR in SAME_EDGE mode. Switching to SAME_EDGE mode removes extra pipelining registers while maintaining the same behaviour. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>		2017-04-18 12:17:39 +02:00
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axi_adcfifo	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
axi_adxcvr	Makefiles: fixed axi_adxcvr/util_adxcvr Makefiles to include interfaces dependancy	2017-02-23 16:16:34 +02:00
axi_dacfifo	all: Update verilog files to verilog-2001	2017-04-13 11:59:55 +03:00
axi_xcvrlb	library: Delete all adi_ip_constraint process call	2017-04-06 12:36:47 +03:00
common	ad_lvds_in: Use "SAME_EDGE" mode	2017-04-18 12:17:39 +02:00
util_adxcvr	library: Delete all adi_ip_constraint process call	2017-04-06 12:36:47 +03:00