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pluto_hdl_adi
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46acdadb92
pluto_hdl_adi
/
library
/
jesd204
/
jesd204_soft_pcs_rx
History
Adrian Costina
1b1edd1b03
jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps
2017-10-25 14:36:54 +01:00
..
8b10b_decoder.v
jesd204: Add soft logic PCS
2017-08-21 11:09:42 +02:00
jesd204_soft_pcs_rx.v
jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps
2017-10-25 14:36:54 +01:00
jesd204_soft_pcs_rx_hw.tcl
jesd204: Added additional input registers to jesd204_soft_pcs_rx, when lane rate is over 10Gbps
2017-10-25 14:36:54 +01:00
pattern_align.v
jesd204: Add soft logic PCS
2017-08-21 11:09:42 +02:00