133 lines
4.3 KiB
VHDL
133 lines
4.3 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2013(c) Analog Devices, Inc.
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-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
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--
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- - Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- - Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in
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-- the documentation and/or other materials provided with the
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-- distribution.
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-- - Neither the name of Analog Devices, Inc. nor the names of its
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-- contributors may be used to endorse or promote products derived
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-- from this software without specific prior written permission.
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-- - The use of this software may or may not infringe the patent rights
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-- of one or more patent holders. This license does not release you
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-- from the requirement that you obtain separate licenses from these
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-- patent holders to use this software.
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-- - Use of the software either in source or binary form, must be run
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-- on or directly connected to an Analog Devices Inc. component.
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--
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-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED.
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--
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-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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entity fifo_synchronizer is
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generic (
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DEPTH : integer := 4;
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WIDTH : integer := 2
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);
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port (
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in_clk : in std_logic;
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in_resetn : in std_logic;
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in_data : in std_logic_vector(WIDTH - 1 downto 0);
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in_tick : in std_logic;
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out_clk : in std_logic;
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out_resetn : in std_logic;
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out_data : out std_logic_vector(WIDTH - 1 downto 0);
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out_tick : out std_logic
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);
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end fifo_synchronizer;
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architecture impl of fifo_synchronizer is
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type DATA_SYNC_FIFO_TYPE is array (0 to DEPTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
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signal fifo: DATA_SYNC_FIFO_TYPE;
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signal rd_addr : natural range 0 to DEPTH - 1;
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signal wr_addr : natural range 0 to DEPTH - 1;
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signal cdc_sync_stage0_tick : std_logic;
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signal cdc_sync_stage1_tick : std_logic;
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signal cdc_sync_stage2_tick : std_logic;
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signal cdc_sync_stage3_tick : std_logic;
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signal tick : std_logic;
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begin
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process (in_clk)
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begin
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if rising_edge(in_clk) then
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if in_tick = '1' then
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cdc_sync_stage0_tick <= not cdc_sync_stage0_tick;
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fifo(wr_addr) <= in_data;
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end if;
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end if;
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end process;
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process (in_clk)
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begin
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if rising_edge(in_clk) then
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if in_resetn = '0' then
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wr_addr <= 0;
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else
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if in_tick = '1' then
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wr_addr <= (wr_addr + 1) mod DEPTH;
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end if;
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end if;
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end if;
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end process;
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process (out_clk)
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begin
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if rising_edge(out_clk) then
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cdc_sync_stage1_tick <= cdc_sync_stage0_tick;
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cdc_sync_stage2_tick <= cdc_sync_stage1_tick;
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cdc_sync_stage3_tick <= cdc_sync_stage2_tick;
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end if;
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end process;
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tick <= cdc_sync_stage2_tick xor cdc_sync_stage3_tick;
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out_tick <= tick;
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process (out_clk)
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begin
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if rising_edge(out_clk) then
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if tick = '1' then
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out_data <= fifo(rd_addr);
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end if;
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end if;
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end process;
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process (out_clk)
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begin
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if rising_edge(out_clk) then
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if out_resetn = '0' then
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rd_addr <= 0;
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else
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if tick = '1' then
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rd_addr <= (rd_addr + 1) mod DEPTH;
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end if;
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end if;
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end if;
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end process;
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end;
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