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pluto_hdl_adi/library/axi_adrv9009
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AndreiGrozav 4ae5a6d3d8 library/IPs: Auto-generate bd.tcl Update 
Remove all bd.tcl and respecting the previous commit, update *_ip.tcl to
auto-generate bd.tcl for:

  - axi_ad5766/axi_ad5766_ip.tcl
  - axi_ad6676/axi_ad6676_ip.tcl
  - axi_ad9122/axi_ad9122_ip.tcl
  - axi_ad9144/axi_ad9144_ip.tcl
  - axi_ad9152/axi_ad9152_ip.tcl
  - axi_ad9162/axi_ad9162_ip.tcl
  - axi_ad9250/axi_ad9250_ip.tcl
  - axi_ad9265/axi_ad9265_ip.tcl
  - axi_ad9361/axi_ad9361_ip.tcl
  - axi_ad9371/axi_ad9371_ip.tcl
  - axi_ad9434/axi_ad9434_ip.tcl
  - axi_ad9467/axi_ad9467_ip.tcl
  - axi_ad9625/axi_ad9625_ip.tcl
  - axi_ad9671/axi_ad9671_ip.tcl
  - axi_ad9680/axi_ad9680_ip.tcl
  - axi_ad9684/axi_ad9684_ip.tcl
  - axi_ad9739a/axi_ad9739a_ip.tcl
  - axi_ad9963/axi_ad9963_ip.tcl
  - axi_adrv9009/axi_adrv9009_ip.tcl
  - axi_fmcadc5_sync/axi_fmcadc5_sync_ip.tcl
  - axi_hdmi_tx/axi_hdmi_tx_ip.tcl
  - xilinx/axi_adxcvr/Makefile
  - xilinx/axi_adxcvr/axi_adxcvr_ip.tcl
  - xilinx/util_adxcvr/Makefile
  - xilinx/util_adxcvr/util_adxcvr_ip.tcl
 		2019-03-30 11:26:11 +02:00
..
Makefile Makefile: update makefiles 2018-12-21 17:32:48 +02:00
axi_adrv9009.v Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_adrv9009_hw.tcl Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_adrv9009_if.v axi_adrv9009: Use the correct clock for the observation path interface 2018-07-09 12:41:52 +01:00
axi_adrv9009_ip.tcl library/IPs: Auto-generate bd.tcl Update 2019-03-30 11:26:11 +02:00
axi_adrv9009_rx.v Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_adrv9009_rx_channel.v axi_adrv9009: Split DATAPATH parameter in multiple parameters. Map the parameters in the CONFIG register 2018-06-29 11:10:39 +03:00
axi_adrv9009_rx_os.v Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_adrv9009_tx.v Add FPGA info parameters flow 2019-03-30 11:26:11 +02:00
axi_adrv9009_tx_channel.v axi_adrv9009: Updates for ad_dds phase acc wrapper 2018-07-18 18:19:30 +03:00