62 lines
1.9 KiB
Tcl
62 lines
1.9 KiB
Tcl
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package require qsys
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source ../scripts/adi_env.tcl
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source ../scripts/adi_ip_alt.tcl
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ad_ip_create util_adcfifo {UTIL ADC FIFO Interface}
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set_module_property ELABORATION_CALLBACK p_util_adcfifo
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# files
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ad_ip_files util_adcfifo [list\
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$ad_hdl_dir/library/common/ad_rst.v \
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$ad_hdl_dir/library/common/ad_axis_inf_rx.v \
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util_adcfifo.v \
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util_adcfifo_constr.sdc]
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# parameters
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ad_ip_parameter DEVICE_FAMILY STRING {Arria 10}
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ad_ip_parameter FPGA_TECHNOLOGY INTEGER 1
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ad_ip_parameter ADC_DATA_WIDTH INTEGER 256
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ad_ip_parameter DMA_DATA_WIDTH INTEGER 64
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ad_ip_parameter DMA_READY_ENABLE INTEGER 1
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ad_ip_parameter DMA_ADDRESS_WIDTH INTEGER 10
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# elaborate
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proc p_util_adcfifo {} {
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# read parameters
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set m_device_family [get_parameter_value "DEVICE_FAMILY"]
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set m_adc_data_width [get_parameter_value "ADC_DATA_WIDTH"]
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set m_dma_addr_width [get_parameter_value "DMA_ADDRESS_WIDTH"]
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set m_dma_data_width [get_parameter_value "DMA_DATA_WIDTH"]
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# altera memory
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add_hdl_instance alt_mem_asym alt_mem_asym
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set_instance_parameter_value alt_mem_asym DEVICE_FAMILY $m_device_family
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set_instance_parameter_value alt_mem_asym A_ADDRESS_WIDTH 0
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set_instance_parameter_value alt_mem_asym A_DATA_WIDTH $m_adc_data_width
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set_instance_parameter_value alt_mem_asym B_ADDRESS_WIDTH $m_dma_addr_width
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set_instance_parameter_value alt_mem_asym B_DATA_WIDTH $m_dma_data_width
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# interfaces
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ad_alt_intf clock adc_clk input 1 adc_clk
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ad_alt_intf reset adc_rst input 1 if_adc_clk
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ad_alt_intf signal adc_wr input 1 valid
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ad_alt_intf signal adc_wdata input ADC_DATA_WIDTH data
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ad_alt_intf signal adc_wovf output 1 ovf
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ad_alt_intf clock dma_clk input 1 clk
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ad_alt_intf signal dma_wr output 1 valid
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ad_alt_intf signal dma_wdata output DMA_DATA_WIDTH data
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ad_alt_intf signal dma_wready input 1 ready
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ad_alt_intf signal dma_xfer_req input 1 xfer_req
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ad_alt_intf signal dma_xfer_status output 4 xfer_status
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}
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