123 lines
4.4 KiB
Verilog
123 lines
4.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// PN monitors
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`timescale 1ns/100ps
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module ad_pnmon (
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// adc interface
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adc_clk,
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adc_valid_in,
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adc_data_in,
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adc_data_pn,
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// pn out of sync and error
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adc_pn_oos,
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adc_pn_err);
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// parameters
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parameter DATA_WIDTH = 16;
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localparam DW = DATA_WIDTH - 1;
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// adc interface
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input adc_clk;
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input adc_valid_in;
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input [DW:0] adc_data_in;
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input [DW:0] adc_data_pn;
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// pn out of sync and error
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output adc_pn_oos;
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output adc_pn_err;
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// internal registers
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reg adc_valid_d = 'd0;
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reg adc_pn_match_d = 'd0;
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reg adc_pn_match_z = 'd0;
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reg adc_pn_err = 'd0;
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reg adc_pn_oos = 'd0;
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reg [ 3:0] adc_pn_oos_count = 'd0;
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// internal signals
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wire adc_pn_match_d_s;
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wire adc_pn_match_z_s;
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wire adc_pn_match_s;
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wire adc_pn_update_s;
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wire adc_pn_err_s;
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// make sure data is not 0, sequence will fail.
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assign adc_pn_match_d_s = (adc_data_in == adc_data_pn) ? 1'b1 : 1'b0;
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assign adc_pn_match_z_s = (adc_data_in == 'd0) ? 1'b0 : 1'b1;
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assign adc_pn_match_s = adc_pn_match_d & adc_pn_match_z;
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assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
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assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
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// pn oos and counters (16 to clear and set).
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always @(posedge adc_clk) begin
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adc_valid_d <= adc_valid_in;
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adc_pn_match_d <= adc_pn_match_d_s;
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adc_pn_match_z <= adc_pn_match_z_s;
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if (adc_valid_d == 1'b1) begin
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adc_pn_err <= adc_pn_err_s;
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if ((adc_pn_update_s == 1'b1) && (adc_pn_oos_count >= 15)) begin
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adc_pn_oos <= ~adc_pn_oos;
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end
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if (adc_pn_update_s == 1'b1) begin
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adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
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end else begin
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adc_pn_oos_count <= 'd0;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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