286 lines
8.5 KiB
Verilog
286 lines
8.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module up_axi (
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// reset and clocks
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up_rstn,
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up_clk,
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// axi4 interface
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up_axi_awvalid,
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up_axi_awaddr,
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up_axi_awready,
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up_axi_wvalid,
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up_axi_wdata,
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up_axi_wstrb,
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up_axi_wready,
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up_axi_bvalid,
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up_axi_bresp,
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up_axi_bready,
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up_axi_arvalid,
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up_axi_araddr,
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up_axi_arready,
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up_axi_rvalid,
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up_axi_rresp,
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up_axi_rdata,
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up_axi_rready,
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// pcore interface
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up_wreq,
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up_waddr,
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up_wdata,
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up_wack,
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up_rreq,
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up_raddr,
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up_rdata,
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up_rack);
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// parameters
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parameter ADDRESS_WIDTH = 14;
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localparam AW = ADDRESS_WIDTH - 1;
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// reset and clocks
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input up_rstn;
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input up_clk;
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// axi4 interface
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input up_axi_awvalid;
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input [31:0] up_axi_awaddr;
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output up_axi_awready;
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input up_axi_wvalid;
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input [31:0] up_axi_wdata;
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input [ 3:0] up_axi_wstrb;
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output up_axi_wready;
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output up_axi_bvalid;
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output [ 1:0] up_axi_bresp;
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input up_axi_bready;
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input up_axi_arvalid;
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input [31:0] up_axi_araddr;
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output up_axi_arready;
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output up_axi_rvalid;
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output [ 1:0] up_axi_rresp;
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output [31:0] up_axi_rdata;
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input up_axi_rready;
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// pcore interface
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output up_wreq;
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output [AW:0] up_waddr;
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output [31:0] up_wdata;
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input up_wack;
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output up_rreq;
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output [AW:0] up_raddr;
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input [31:0] up_rdata;
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input up_rack;
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// internal registers
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reg up_axi_awready = 'd0;
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reg up_axi_wready = 'd0;
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reg up_axi_bvalid = 'd0;
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reg up_wsel = 'd0;
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reg up_wreq = 'd0;
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reg [AW:0] up_waddr = 'd0;
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reg [31:0] up_wdata = 'd0;
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reg [ 2:0] up_wcount = 'd0;
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reg up_wack_int = 'd0;
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reg up_axi_arready = 'd0;
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reg up_axi_rvalid = 'd0;
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reg [31:0] up_axi_rdata = 'd0;
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reg up_rsel = 'd0;
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reg up_rreq = 'd0;
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reg [AW:0] up_raddr = 'd0;
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reg [ 3:0] up_rcount = 'd0;
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reg up_rack_int = 'd0;
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reg [31:0] up_rdata_int = 'd0;
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reg up_rack_int_d = 'd0;
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reg [31:0] up_rdata_int_d = 'd0;
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// write channel interface
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assign up_axi_bresp = 2'd0;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_axi_awready <= 'd0;
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up_axi_wready <= 'd0;
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up_axi_bvalid <= 'd0;
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end else begin
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if (up_axi_awready == 1'b1) begin
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up_axi_awready <= 1'b0;
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end else if (up_wack_int == 1'b1) begin
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up_axi_awready <= 1'b1;
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end
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if (up_axi_wready == 1'b1) begin
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up_axi_wready <= 1'b0;
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end else if (up_wack_int == 1'b1) begin
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up_axi_wready <= 1'b1;
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end
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if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
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up_axi_bvalid <= 1'b0;
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end else if (up_wack_int == 1'b1) begin
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up_axi_bvalid <= 1'b1;
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end
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_wsel <= 'd0;
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up_wreq <= 'd0;
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up_waddr <= 'd0;
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up_wdata <= 'd0;
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up_wcount <= 'd0;
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end else begin
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if (up_wsel == 1'b1) begin
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if ((up_axi_bready == 1'b1) && (up_axi_bvalid == 1'b1)) begin
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up_wsel <= 1'b0;
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end
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up_wreq <= 1'b0;
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up_waddr <= up_waddr;
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up_wdata <= up_wdata;
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up_wcount <= up_wcount + 1'b1;
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end else begin
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up_wsel <= up_axi_awvalid & up_axi_wvalid;
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up_wreq <= up_axi_awvalid & up_axi_wvalid;
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up_waddr <= up_axi_awaddr[AW+2:2];
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up_wdata <= up_axi_wdata;
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up_wcount <= 3'd0;
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end
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_wack_int <= 'd0;
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end else begin
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if ((up_wcount == 3'h7) && (up_wack == 1'b0)) begin
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up_wack_int <= 1'b1;
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end else if (up_wsel == 1'b1) begin
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up_wack_int <= up_wack;
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end
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end
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end
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// read channel interface
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assign up_axi_rresp = 2'd0;
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_axi_arready <= 'd0;
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up_axi_rvalid <= 'd0;
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up_axi_rdata <= 'd0;
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end else begin
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if (up_axi_arready == 1'b1) begin
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up_axi_arready <= 1'b0;
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end else if (up_rack_int == 1'b1) begin
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up_axi_arready <= 1'b1;
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end
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if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
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up_axi_rvalid <= 1'b0;
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up_axi_rdata <= 32'd0;
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end else if (up_rack_int_d == 1'b1) begin
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up_axi_rvalid <= 1'b1;
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up_axi_rdata <= up_rdata_int_d;
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end
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 1'b0) begin
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up_rsel <= 'd0;
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up_rreq <= 'd0;
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up_raddr <= 'd0;
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up_rcount <= 'd0;
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end else begin
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if (up_rsel == 1'b1) begin
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if ((up_axi_rready == 1'b1) && (up_axi_rvalid == 1'b1)) begin
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up_rsel <= 1'b0;
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end
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up_rreq <= 1'b0;
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up_raddr <= up_raddr;
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end else begin
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up_rsel <= up_axi_arvalid;
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up_rreq <= up_axi_arvalid;
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up_raddr <= up_axi_araddr[AW+2:2];
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end
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if (up_rack_int == 1'b1) begin
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up_rcount <= 4'd0;
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end else if (up_rcount[3] == 1'b1) begin
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up_rcount <= up_rcount + 1'b1;
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end else if (up_rreq == 1'b1) begin
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up_rcount <= 4'd8;
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end
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end
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end
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_rack_int <= 'd0;
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up_rdata_int <= 'd0;
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up_rack_int_d <= 'd0;
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up_rdata_int_d <= 'd0;
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end else begin
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if ((up_rcount == 4'hf) && (up_rack == 1'b0)) begin
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up_rack_int <= 1'b1;
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up_rdata_int <= {2{16'hdead}};
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end else begin
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up_rack_int <= up_rack;
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up_rdata_int <= up_rdata;
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end
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up_rack_int_d <= up_rack_int;
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up_rdata_int_d <= up_rdata_int;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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