Istvan Csomortani 472b12feb7 ad_rst: Update the reset synchronizer module ... For a proper reset synchronization, the asynchronous reset signal should be connected to the reset pins of the two synchronizer flop, and the data input of the first flop should be connected to VCC. In the first stage we're synchronizing just the reset de-assertion, avoiding the scenario when different parts of the design are reseting at different time, causing unwanted behaviours. In the second stage we're synchronizing the reset assertion. The module expects an ACTIVE_HIGH input reset signal, and provides an ACTIVE_LOW (rstn) and an ACTIVE_HIGH (rst) synchronized reset output signal.		2018-08-06 21:24:41 +03:00
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alt_ifconv	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
alt_mem_asym	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
alt_mul	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
alt_serdes	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
ad_dcfilter.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
ad_mul.v	ad_mul.v: Add parameters for A and B input widths	2018-07-18 18:19:30 +03:00
up_clock_mon_constr.sdc	up_clock_mon- name changes	2017-06-06 11:36:18 -04:00
up_rst_constr.sdc	ad_rst: Update the reset synchronizer module	2018-08-06 21:24:41 +03:00
up_xfer_cntrl_constr.sdc	constraints: Split the regmap CDC constraint into separate file	2017-05-25 15:12:16 +03:00
up_xfer_status_constr.sdc	constraints: Split the regmap CDC constraint into separate file	2017-05-25 15:12:16 +03:00