41 lines
1.5 KiB
Makefile
41 lines
1.5 KiB
Makefile
####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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LIBRARY_NAME := axi_ad9684
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GENERIC_DEPS += ../common/ad_datafmt.v
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GENERIC_DEPS += ../common/ad_pnmon.v
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GENERIC_DEPS += ../common/ad_rst.v
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GENERIC_DEPS += ../common/up_adc_channel.v
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GENERIC_DEPS += ../common/up_adc_common.v
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GENERIC_DEPS += ../common/up_axi.v
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GENERIC_DEPS += ../common/up_clock_mon.v
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GENERIC_DEPS += ../common/up_delay_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_cntrl.v
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GENERIC_DEPS += ../common/up_xfer_status.v
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GENERIC_DEPS += axi_ad9684.v
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GENERIC_DEPS += axi_ad9684_channel.v
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GENERIC_DEPS += axi_ad9684_if.v
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GENERIC_DEPS += axi_ad9684_pnmon.v
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XILINX_DEPS += ../xilinx/common/ad_mmcm_drp.v
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XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
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XILINX_DEPS += ../xilinx/common/ad_serdes_clk.v
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XILINX_DEPS += ../xilinx/common/ad_serdes_in.v
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XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
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XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
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XILINX_DEPS += axi_ad9684_constr.xdc
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XILINX_DEPS += axi_ad9684_ip.tcl
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ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
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ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
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ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
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ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
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ALTERA_DEPS += axi_ad9684_constr.sdc
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ALTERA_DEPS += axi_ad9684_hw.tcl
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include ../scripts/library.mk
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