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The util_cpack2 core is similar to the util_upack core. It packs, or interleaves, a data from multiple ports into a single data. Ports can optionally be enabled or disabled. On the input side the cpack2 core uses a multi-port FIFO interface. There is a single data write signal (fifo_wr_en) for all ports. But each port can be individually enabled or disabled using the enable signals. On the output side the cpack2 core uses a single port FIFO interface. When data is available on the output interface the data write signal (packed_fifo_wr_en). Data on the packed_fifo_wr_data signal is only valid when packed_fifo_wr_en is asserted. At other times the content is undefined. The cpack2 core offers no back-pressure. If data is not consumed when it is made available it will be lost. Data from the input ports is accumulated inside the cpack2 core and if enough data is available to produce a full output vector the data is forwarded. This core is build using the common pack infrastructure. The core that is specific to the cpack2 core is mainly only responsible for generating the control signals for the external interfaces. The core is accompanied by a test bench that verifies correct behavior for all possible combinations of enable masks. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| Makefile | ||
| util_cpack2.v | ||
| util_cpack2_hw.tcl | ||
| util_cpack2_impl.v | ||
| util_cpack2_ip.tcl | ||