157afcbc33
The tb_base.v verilog files does not contain a full module definition, just some plain test code. In general the files is sourced inside the test bench main module. As is, defining a timescale in these files will generate an error, because timescale directive can not be inside a module. Delete all the timescale directive from these files. |
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| .. | ||
| .gitignore | ||
| axi_jesd204_rx_regmap_tb | ||
| axi_jesd204_rx_regmap_tb.v | ||
| axi_jesd204_tx_regmap_tb | ||
| axi_jesd204_tx_regmap_tb.v | ||
| loopback_tb | ||
| loopback_tb.v | ||
| run_tb.sh | ||
| rx_cgs_tb | ||
| rx_cgs_tb.v | ||
| rx_ctrl_tb | ||
| rx_ctrl_tb.v | ||
| rx_lane_tb | ||
| rx_lane_tb.v | ||
| rx_tb | ||
| rx_tb.v | ||
| scrambler_tb | ||
| scrambler_tb.v | ||
| soft_pcs_8b10b_sequence_tb | ||
| soft_pcs_8b10b_sequence_tb.v | ||
| soft_pcs_8b10b_table_tb | ||
| soft_pcs_8b10b_table_tb.v | ||
| soft_pcs_loopback_tb | ||
| soft_pcs_loopback_tb.v | ||
| soft_pcs_pattern_align_tb | ||
| soft_pcs_pattern_align_tb.v | ||
| tb_base.v | ||
| tx_ctrl_phase_tb | ||
| tx_ctrl_phase_tb.v | ||
| tx_tb | ||
| tx_tb.v | ||