200 lines
6.6 KiB
Verilog
Executable File
200 lines
6.6 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_cpack_dsf (
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// adc interface
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adc_clk,
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adc_valid,
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adc_enable,
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adc_data,
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// dma interface
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adc_dsf_valid,
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adc_dsf_sync,
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adc_dsf_data);
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// parameters
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parameter CH_DW = 32;
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parameter CH_ICNT = 4;
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parameter CH_MCNT = 8;
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parameter P_CNT = 4;
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localparam CH_DCNT = P_CNT - CH_ICNT;
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localparam I_WIDTH = CH_DW*CH_ICNT;
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localparam P_WIDTH = CH_DW*P_CNT;
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localparam M_WIDTH = CH_DW*CH_MCNT;
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// adc interface
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input adc_clk;
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input adc_valid;
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input adc_enable;
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input [(I_WIDTH-1):0] adc_data;
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// dma interface
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output adc_dsf_valid;
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output adc_dsf_sync;
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output [(P_WIDTH-1):0] adc_dsf_data;
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// internal registers
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reg [ 2:0] adc_samples_int = 'd0;
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reg [(M_WIDTH-1):0] adc_data_int = 'd0;
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reg adc_dsf_enable = 'd0;
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reg adc_dsf_valid_int = 'd0;
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reg adc_dsf_sync_int = 'd0;
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reg [(P_WIDTH-1):0] adc_dsf_data_int = 'd0;
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reg adc_dsf_valid = 'd0;
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reg adc_dsf_sync = 'd0;
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reg [(P_WIDTH-1):0] adc_dsf_data = 'd0;
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// internal signals
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wire [(M_WIDTH-1):0] adc_data_s;
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// bypass
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generate
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if (CH_ICNT == P_CNT) begin
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assign adc_data_s = 'd0;
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always @(posedge adc_clk) begin
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adc_samples_int <= 'd0;
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adc_data_int <= 'd0;
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adc_dsf_enable <= 'd0;
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adc_dsf_valid_int <= 'd0;
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adc_dsf_sync_int <= 'd0;
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adc_dsf_data_int <= 'd0;
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if (adc_enable == 1'b1) begin
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adc_dsf_valid <= adc_valid;
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adc_dsf_sync <= 1'b1;
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adc_dsf_data <= adc_data;
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end else begin
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adc_dsf_valid <= 'b0;
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adc_dsf_sync <= 'b0;
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adc_dsf_data <= 'd0;
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end
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end
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end
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endgenerate
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// data store & forward
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generate
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if (P_CNT > CH_ICNT) begin
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assign adc_data_s[(M_WIDTH-1):I_WIDTH] = 'd0;
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assign adc_data_s[(I_WIDTH-1):0] = adc_data;
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always @(posedge adc_clk) begin
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if (adc_valid == 1'b1) begin
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if (adc_samples_int >= CH_DCNT) begin
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adc_samples_int <= adc_samples_int - CH_DCNT;
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end else begin
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adc_samples_int <= adc_samples_int + CH_ICNT;
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end
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adc_data_int <= {adc_data_s[(I_WIDTH-1):0],
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adc_data_int[(M_WIDTH-1):I_WIDTH]};
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end
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end
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always @(posedge adc_clk) begin
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adc_dsf_enable <= adc_enable;
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if (adc_samples_int >= CH_DCNT) begin
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adc_dsf_valid_int <= adc_valid;
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end else begin
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adc_dsf_valid_int <= 1'b0;
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end
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if (adc_dsf_sync_int == 1'b1) begin
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if (adc_dsf_valid_int == 1'b1) begin
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adc_dsf_sync_int <= 1'b0;
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end
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end else begin
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if (adc_samples_int == 3'd0) begin
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adc_dsf_sync_int <= 1'b1;
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end
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end
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end
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always @(posedge adc_clk) begin
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if (adc_valid == 1'b1) begin
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case (adc_samples_int)
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3'b111: adc_dsf_data_int <= {adc_data_s[((CH_DW*1)-1):0],
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adc_data_int[((CH_DW*8)-1):(CH_DW*1)]};
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3'b110: adc_dsf_data_int <= {adc_data_s[((CH_DW*2)-1):0],
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adc_data_int[((CH_DW*8)-1):(CH_DW*2)]};
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3'b101: adc_dsf_data_int <= {adc_data_s[((CH_DW*3)-1):0],
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adc_data_int[((CH_DW*8)-1):(CH_DW*3)]};
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3'b100: adc_dsf_data_int <= {adc_data_s[((CH_DW*4)-1):0],
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adc_data_int[((CH_DW*8)-1):(CH_DW*4)]};
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3'b011: adc_dsf_data_int <= {adc_data_s[((CH_DW*5)-1):0],
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adc_data_int[((CH_DW*8)-1):(CH_DW*5)]};
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3'b010: adc_dsf_data_int <= {adc_data_s[((CH_DW*6)-1):0],
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adc_data_int[((CH_DW*8)-1):(CH_DW*6)]};
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3'b001: adc_dsf_data_int <= {adc_data_s[((CH_DW*7)-1):0],
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adc_data_int[((CH_DW*8)-1):(CH_DW*7)]};
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3'b000: adc_dsf_data_int <= adc_data_s;
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default: adc_dsf_data_int <= 'd0;
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endcase
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end
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end
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always @(posedge adc_clk) begin
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if (adc_enable == 1'b1) begin
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adc_dsf_valid <= adc_dsf_valid_int;
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adc_dsf_sync <= adc_dsf_sync_int;
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adc_dsf_data <= adc_dsf_data_int[(P_WIDTH-1):0];
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end else begin
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adc_dsf_valid <= 'b0;
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adc_dsf_sync <= 'b0;
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adc_dsf_data <= 'd0;
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end
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end
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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