42 lines
1.5 KiB
Plaintext
42 lines
1.5 KiB
Plaintext
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create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}]
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create_clock -period "8.139 ns" -name ref_clk0_122mhz [get_ports {ref_clk0}]
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create_clock -period "8.139 ns" -name ref_clk1_122mhz [get_ports {ref_clk1}]
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derive_pll_clocks
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derive_clock_uncertainty
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]
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set_false_path -from [get_clocks {sys_clk_100mhz}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
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-through [get_nets *altera_jesd204_tx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|tx_dac_clk}]\
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-through [get_nets *altera_jesd204_tx_ctl_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_clk}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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set_false_path -from [get_clocks {i_system_bd|xcvr_pll|rx_adc_os_clk}]\
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-through [get_nets *altera_jesd204_rx_csr_inst*]\
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-to [get_clocks {sys_clk_100mhz}]
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