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Adrian Costina 050f17e034 a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2 2015-01-23 12:30:16 +02:00
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system_project.tcl a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2 2015-01-23 12:30:16 +02:00
system_timing.tcl a5gt: ethernet-fpga lvds mode 2014-09-04 11:19:25 -04:00
system_top.v a5gt3: common: corrected naming in pin assignments. added reset signal from FPGA2 2015-01-23 12:30:16 +02:00