pluto_hdl_adi/library/axi_ad9361/axi_ad9361_tdd_if.v

136 lines
4.4 KiB
Verilog

// ***************************************************************************
// ***************************************************************************
// Copyright 2015(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
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// distribution.
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// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps
module axi_ad9361_tdd_if(
// clock
clk,
rst,
// control signals from the tdd control
tdd_rx_vco_en,
tdd_tx_vco_en,
tdd_rx_rf_en,
tdd_tx_rf_en,
// device interface
ad9361_txnrx,
ad9361_enable,
// interface status
ad9361_tdd_status
);
// parameters
parameter MODE_OF_ENABLE = 0;
localparam PULSE_MODE = 0;
localparam LEVEL_MODE = 1;
// clock
input clk;
input rst;
// control signals from the tdd control
input tdd_rx_vco_en;
input tdd_tx_vco_en;
input tdd_rx_rf_en;
input tdd_tx_rf_en;
// device interface
output ad9361_txnrx;
output ad9361_enable;
// interface status
output [ 7:0] ad9361_tdd_status;
// internal registers
reg tdd_rx_rf_en_d = 1'b0;
reg tdd_tx_rf_en_d = 1'b0;
reg tdd_vco_overlap = 1'b0;
reg tdd_rf_overlap = 1'b0;
wire ad9361_txnrx_s;
wire ad9361_enable_s;
// just one VCO can be enabled at a time
assign ad9361_txnrx_s = tdd_tx_vco_en;
always @(posedge clk) begin
tdd_rx_rf_en_d <= tdd_rx_rf_en;
tdd_tx_rf_en_d <= tdd_tx_rf_en;
end
assign ad9361_enable_s = (MODE_OF_ENABLE == PULSE_MODE) ?
((~tdd_rx_rf_en_d & tdd_rx_rf_en) | (tdd_rx_rf_en_d & ~tdd_rx_rf_en) |
(~tdd_tx_rf_en_d & tdd_tx_rf_en) | (tdd_tx_rf_en_d & ~tdd_tx_rf_en)) :
(tdd_rx_rf_en | tdd_tx_rf_en);
always @(posedge clk) begin
if(rst == 1'b1) begin
tdd_vco_overlap <= 1'b0;
tdd_rf_overlap <= 1'b0;
end else begin
tdd_vco_overlap <= tdd_rx_vco_en & tdd_tx_vco_en;
tdd_rf_overlap <= tdd_rx_rf_en & tdd_tx_rf_en;
end
end
assign ad9361_tdd_status = {6'b0, tdd_rf_overlap, tdd_vco_overlap};
assign ad9361_txnrx = ad9361_txnrx_s;
assign ad9361_enable = ad9361_enable_s;
endmodule