214 lines
6.7 KiB
Verilog
214 lines
6.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// software programmable clock generator (still needs a reference input!)
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module axi_clkgen #(
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parameter ID = 0,
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parameter DEVICE_TYPE = 0,
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parameter CLKSEL_EN = 0,
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parameter real CLKIN_PERIOD = 5.000,
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parameter real CLKIN2_PERIOD = 5.000,
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parameter integer VCO_DIV = 11,
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parameter real VCO_MUL = 49.000,
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parameter real CLK0_DIV = 6.000,
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parameter real CLK0_PHASE = 0.000,
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parameter integer CLK1_DIV = 6,
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parameter real CLK1_PHASE = 0.000) (
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// clocks
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input clk,
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input clk2,
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output clk_0,
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output clk_1,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [15:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [15:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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// reset and clocks
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wire mmcm_rst;
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wire clk_sel_s;
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wire up_clk_sel_s;
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire up_drp_sel_s;
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wire up_drp_wr_s;
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wire [11:0] up_drp_addr_s;
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wire [15:0] up_drp_wdata_s;
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wire [15:0] up_drp_rdata_s;
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wire up_drp_ready_s;
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wire up_drp_locked_s;
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s;
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wire up_rack_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// processor interface
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up_clkgen #(
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.ID(ID)
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) i_up_clkgen (
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.mmcm_rst (mmcm_rst),
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.clk_sel (up_clk_sel_s),
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.up_drp_sel (up_drp_sel_s),
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.up_drp_wr (up_drp_wr_s),
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.up_drp_addr (up_drp_addr_s),
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.up_drp_wdata (up_drp_wdata_s),
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.up_drp_rdata (up_drp_rdata_s),
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.up_drp_ready (up_drp_ready_s),
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.up_drp_locked (up_drp_locked_s),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// If CLKSEL_EN is not active, the clk0 port of the MMCM is used, this
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// should be used when the MMCM has only one active clock source
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generate if (CLKSEL_EN == 1) begin
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assign clk_sel_s = up_clk_sel_s;
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end else begin
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assign clk_sel_s = 1'b1;
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end
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endgenerate
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// mmcm instantiations
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ad_mmcm_drp #(
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.MMCM_DEVICE_TYPE (DEVICE_TYPE),
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.MMCM_CLKIN_PERIOD (CLKIN_PERIOD),
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.MMCM_CLKIN2_PERIOD (CLKIN2_PERIOD),
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.MMCM_VCO_DIV (VCO_DIV),
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.MMCM_VCO_MUL (VCO_MUL),
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.MMCM_CLK0_DIV (CLK0_DIV),
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.MMCM_CLK0_PHASE (CLK0_PHASE),
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.MMCM_CLK1_DIV (CLK1_DIV),
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.MMCM_CLK1_PHASE (CLK1_PHASE))
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i_mmcm_drp (
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.clk (clk),
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.clk2 (clk2),
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.clk_sel(clk_sel_s),
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.mmcm_rst (mmcm_rst),
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.mmcm_clk_0 (clk_0),
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.mmcm_clk_1 (clk_1),
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.mmcm_clk_2 (),
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.up_clk (up_clk),
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.up_rstn (up_rstn),
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.up_drp_sel (up_drp_sel_s),
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.up_drp_wr (up_drp_wr_s),
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.up_drp_addr (up_drp_addr_s),
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.up_drp_wdata (up_drp_wdata_s),
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.up_drp_rdata (up_drp_rdata_s),
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.up_drp_ready (up_drp_ready_s),
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.up_drp_locked (up_drp_locked_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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