242 lines
6.7 KiB
Verilog
242 lines
6.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module util_axis_fifo #(
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parameter DATA_WIDTH = 64,
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parameter ASYNC_CLK = 1,
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parameter ADDRESS_WIDTH = 4,
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parameter S_AXIS_REGISTERED = 1
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) (
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input m_axis_aclk,
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input m_axis_aresetn,
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input m_axis_ready,
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output m_axis_valid,
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output [DATA_WIDTH-1:0] m_axis_data,
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output [ADDRESS_WIDTH:0] m_axis_level,
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input s_axis_aclk,
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input s_axis_aresetn,
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output s_axis_ready,
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input s_axis_valid,
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input [DATA_WIDTH-1:0] s_axis_data,
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output s_axis_empty,
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output [ADDRESS_WIDTH:0] s_axis_room
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);
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generate if (ADDRESS_WIDTH == 0) begin
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reg [DATA_WIDTH-1:0] cdc_sync_fifo_ram;
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reg s_axis_waddr = 1'b0;
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reg m_axis_raddr = 1'b0;
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wire m_axis_waddr;
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wire s_axis_raddr;
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sync_bits #(
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.NUM_OF_BITS(1),
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.ASYNC_CLK(ASYNC_CLK)
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) i_waddr_sync (
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.out_clk(m_axis_aclk),
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.out_resetn(m_axis_aresetn),
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.in(s_axis_waddr),
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.out(m_axis_waddr)
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);
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sync_bits #(
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.NUM_OF_BITS(1),
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.ASYNC_CLK(ASYNC_CLK)
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) i_raddr_sync (
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.out_clk(s_axis_aclk),
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.out_resetn(s_axis_aresetn),
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.in(m_axis_raddr),
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.out(s_axis_raddr)
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);
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assign m_axis_valid = m_axis_raddr != m_axis_waddr;
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assign m_axis_level = m_axis_valid;
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assign s_axis_ready = s_axis_raddr == s_axis_waddr;
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assign s_axis_empty = s_axis_ready;
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assign s_axis_room = s_axis_ready;
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always @(posedge s_axis_aclk) begin
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if (s_axis_ready == 1'b1 && s_axis_valid == 1'b1)
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cdc_sync_fifo_ram <= s_axis_data;
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end
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always @(posedge s_axis_aclk) begin
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if (s_axis_aresetn == 1'b0) begin
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s_axis_waddr <= 1'b0;
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end else begin
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if (s_axis_ready & s_axis_valid) begin
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s_axis_waddr <= s_axis_waddr + 1'b1;
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end
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end
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end
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always @(posedge m_axis_aclk) begin
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if (m_axis_aresetn == 1'b0) begin
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m_axis_raddr <= 1'b0;
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end else begin
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if (m_axis_valid & m_axis_ready)
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m_axis_raddr <= m_axis_raddr + 1'b1;
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end
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end
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assign m_axis_data = cdc_sync_fifo_ram;
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end else begin
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reg [DATA_WIDTH-1:0] ram[0:2**ADDRESS_WIDTH-1];
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wire [ADDRESS_WIDTH-1:0] s_axis_waddr;
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wire [ADDRESS_WIDTH-1:0] m_axis_raddr;
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wire _m_axis_ready;
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wire _m_axis_valid;
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wire s_mem_write;
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wire m_mem_read;
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reg valid;
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always @(posedge m_axis_aclk) begin
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if (m_axis_aresetn == 1'b0) begin
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valid <= 1'b0;
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end else begin
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if (_m_axis_valid)
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valid <= 1'b1;
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else if (m_axis_ready)
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valid <= 1'b0;
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end
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end
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assign s_mem_write = s_axis_ready & s_axis_valid;
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assign m_mem_read = (~valid || m_axis_ready) && _m_axis_valid;
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if (ASYNC_CLK == 1) begin
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// The assumption is that in this mode the S_AXIS_REGISTERED is 1
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fifo_address_gray_pipelined #(
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.ADDRESS_WIDTH(ADDRESS_WIDTH)
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) i_address_gray (
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.m_axis_aclk(m_axis_aclk),
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.m_axis_aresetn(m_axis_aresetn),
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.m_axis_ready(_m_axis_ready),
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.m_axis_valid(_m_axis_valid),
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.m_axis_raddr(m_axis_raddr),
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.m_axis_level(m_axis_level),
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.s_axis_aclk(s_axis_aclk),
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.s_axis_aresetn(s_axis_aresetn),
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.s_axis_ready(s_axis_ready),
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.s_axis_valid(s_axis_valid),
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.s_axis_empty(s_axis_empty),
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.s_axis_waddr(s_axis_waddr),
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.s_axis_room(s_axis_room)
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);
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// When the clocks are asynchronous instantiate a block RAM
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// regardless of the requested size to make sure we threat the
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// clock crossing correctly
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ad_mem #(
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.DATA_WIDTH (DATA_WIDTH),
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.ADDRESS_WIDTH (ADDRESS_WIDTH))
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i_mem (
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.clka(s_axis_aclk),
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.wea(s_mem_write),
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.addra(s_axis_waddr),
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.dina(s_axis_data),
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.clkb(m_axis_aclk),
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.reb(m_mem_read),
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.addrb(m_axis_raddr),
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.doutb(m_axis_data)
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);
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assign _m_axis_ready = ~valid || m_axis_ready;
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assign m_axis_valid = valid;
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end else begin
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fifo_address_sync #(
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.ADDRESS_WIDTH(ADDRESS_WIDTH)
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) i_address_sync (
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.clk(m_axis_aclk),
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.resetn(m_axis_aresetn),
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.m_axis_ready(_m_axis_ready),
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.m_axis_valid(_m_axis_valid),
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.m_axis_raddr(m_axis_raddr),
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.m_axis_level(m_axis_level),
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.s_axis_ready(s_axis_ready),
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.s_axis_valid(s_axis_valid),
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.s_axis_empty(s_axis_empty),
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.s_axis_waddr(s_axis_waddr),
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.s_axis_room(s_axis_room)
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);
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// When the clocks are synchronous use behavioral modeling for the SDP RAM
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// Let the synthesizer decide what to infer (distributed or block RAM)
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always @(posedge s_axis_aclk) begin
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if (s_mem_write)
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ram[s_axis_waddr] <= s_axis_data;
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end
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if (S_AXIS_REGISTERED == 1) begin
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reg [DATA_WIDTH-1:0] data;
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always @(posedge m_axis_aclk) begin
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if (m_mem_read)
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data <= ram[m_axis_raddr];
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end
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assign _m_axis_ready = ~valid || m_axis_ready;
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assign m_axis_data = data;
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assign m_axis_valid = valid;
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end else begin
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assign _m_axis_ready = m_axis_ready;
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assign m_axis_valid = _m_axis_valid;
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assign m_axis_data = ram[m_axis_raddr];
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end
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end
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end endgenerate
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endmodule
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