Istvan Csomortani 472b12feb7 ad_rst: Update the reset synchronizer module ... For a proper reset synchronization, the asynchronous reset signal should be connected to the reset pins of the two synchronizer flop, and the data input of the first flop should be connected to VCC. In the first stage we're synchronizing just the reset de-assertion, avoiding the scenario when different parts of the design are reseting at different time, causing unwanted behaviours. In the second stage we're synchronizing the reset assertion. The module expects an ACTIVE_HIGH input reset signal, and provides an ACTIVE_LOW (rstn) and an ACTIVE_HIGH (rst) synchronized reset output signal.		2018-08-06 21:24:41 +03:00
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axi_adcfifo	ad_mem_asym: Improve the implementation of the asymmetric RAM	2018-08-06 17:29:05 +03:00
axi_adxcvr	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
axi_dacfifo	ad_mem_asym: Improve the implementation of the asymmetric RAM	2018-08-06 17:29:05 +03:00
axi_xcvrlb	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
common	ad_rst: Update the reset synchronizer module	2018-08-06 21:24:41 +03:00
util_adxcvr	xilinx: util_adxcvr: Add support for lane polarity inversion	2018-05-02 09:37:23 +02:00