Adrian Costina e445fbe04f adrv9009: Improved data throughput and DAC FIFO size ... Moved XCVR related connections to HP0, where the HP shares the MUX with the Video DMA HP1 and HP2 are used for RX OS and RX DMAs, sharing the MUX. Usually they shouldn't run at the same time. HP3 is used for TX DMA, sharing the MUX with the FPD DMA controller All HPx and DMA buswidths have been increased to 128 bits The HPx-DMA clock has been increased to 300 MHz DAC FIFO address size has been increased to 17		2018-05-14 11:33:04 +03:00
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adrv9009_bd.tcl	adrv9009: Improved data throughput and DAC FIFO size	2018-05-14 11:33:04 +03:00