315 lines
11 KiB
Verilog
315 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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// hps-ddr
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output [ 14:0] ddr3_a,
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output [ 2:0] ddr3_ba,
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output ddr3_reset_n,
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output ddr3_ck_p,
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output ddr3_ck_n,
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output ddr3_cke,
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output ddr3_cs_n,
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output ddr3_ras_n,
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output ddr3_cas_n,
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output ddr3_we_n,
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inout [ 31:0] ddr3_dq,
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inout [ 3:0] ddr3_dqs_p,
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inout [ 3:0] ddr3_dqs_n,
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output [ 3:0] ddr3_dm,
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output ddr3_odt,
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input ddr3_rzq,
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// hps-ethernet
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output eth1_tx_clk,
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output eth1_tx_ctl,
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output [ 3:0] eth1_tx_d,
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input eth1_rx_clk,
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input eth1_rx_ctl,
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input [ 3:0] eth1_rx_d,
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output eth1_mdc,
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inout eth1_mdio,
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// hps-qspi
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output qspi_ss0,
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output qspi_clk,
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inout [ 3:0] qspi_io,
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// hps-sdio
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output sdio_clk,
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inout sdio_cmd,
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inout [ 3:0] sdio_d,
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// hps-usb
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input usb1_clk,
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output usb1_stp,
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input usb1_dir,
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input usb1_nxt,
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inout [ 7:0] usb1_d,
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// hps-uart
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input uart0_rx,
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output uart0_tx,
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// board gpio
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inout [ 35:0] gpio_0,
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inout [ 35:0] gpio_1,
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inout [ 13:0] gpio_bd,
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inout hps_gpio_led,
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inout hps_gpio_pb,
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// adxl345 iic interface
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inout adxl345_scl,
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inout adxl345_sda,
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inout adxl345_int,
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// ltc connector iic/spi interface
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inout ltc_i2c_spi_sel,
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inout ltc_i2c_scl,
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inout ltc_i2c_sda,
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output ltc_spi_csn,
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output ltc_spi_clk,
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output ltc_spi_mosi,
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input ltc_spi_miso,
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output hdmi_out_clk,
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output hdmi_vsync,
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output hdmi_hsync,
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output hdmi_data_e,
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output [ 23:0] hdmi_data,
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inout hdmi_i2c_scl,
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inout hdmi_i2c_sda,
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inout hdmi_i2s,
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inout hdmi_lrclk,
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inout hdmi_mclk,
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inout hdmi_sclk,
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// arduino interface
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inout arduino_i2c_scl,
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inout arduino_i2c_sda,
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output [ 3:0] arduino_spi_csn,
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output arduino_spi_clk,
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output arduino_spi_mosi,
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input arduino_spi_miso,
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inout arduino_reset_n,
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inout [ 6:0] arduino_gpio);
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// internal signals
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wire sys_resetn;
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wire i2c2_scl_oe;
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wire i2c2_scl;
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wire i2c2_sda_oe;
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wire i2c2_sda;
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wire i2c3_scl_oe;
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wire i2c3_scl;
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wire i2c3_sda_oe;
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wire i2c3_sda;
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wire hdmi_valid_s;
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wire hdmi_ready_s;
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wire [ 63:0] hdmi_data_s;
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wire hdmi_fs;
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// instantiations
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ALT_IOBUF iobuf_i2c2_scl (
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.i (1'b0),
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.oe (i2c2_scl_oe),
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.o (i2c2_scl),
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.io (arduino_i2c_scl));
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ALT_IOBUF iobuf_i2c2_sda (
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.i (1'b0),
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.oe (i2c2_sda_oe),
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.o (i2c2_sda),
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.io (arduino_i2c_sda));
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ALT_IOBUF iobuf_i2c3_scl (
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.i (1'b0),
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.oe (i2c3_scl_oe),
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.o (i2c3_scl),
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.io (hdmi_i2c_scl));
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ALT_IOBUF iobuf_i2c3_sda (
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.i (1'b0),
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.oe (i2c3_sda_oe),
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.o (i2c3_sda),
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.io (hdmi_i2c_sda));
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system_bd i_system_bd (
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.sys_clk_clk (sys_clk),
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.sys_gpio_0_0_export (gpio_0[31:0]),
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.sys_gpio_0_1_export (gpio_0[35:32]),
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.sys_gpio_1_0_export (gpio_1[31:0]),
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.sys_gpio_1_1_export (gpio_1[35:32]),
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.sys_gpio_arduino_export ({arduino_reset_n, arduino_gpio}),
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.sys_gpio_bd_export (gpio_bd),
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.sys_hps_h2f_reset_reset_n (sys_resetn),
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.sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk),
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.sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]),
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.sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]),
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.sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]),
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.sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]),
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.sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]),
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.sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio),
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.sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc),
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.sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl),
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.sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl),
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.sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk),
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.sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]),
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.sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]),
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.sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]),
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.sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]),
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.sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]),
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.sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]),
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.sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]),
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.sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0),
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.sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk),
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.sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd),
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.sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]),
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.sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]),
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.sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk),
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.sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]),
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.sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]),
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.sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]),
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.sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]),
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.sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]),
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.sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]),
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.sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]),
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.sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]),
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.sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]),
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.sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]),
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.sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk),
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.sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp),
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.sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir),
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.sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt),
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.sys_hps_hps_io_hps_io_spim1_inst_CLK (ltc_spi_clk),
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.sys_hps_hps_io_hps_io_spim1_inst_MOSI (ltc_spi_mosi),
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.sys_hps_hps_io_hps_io_spim1_inst_MISO (ltc_spi_miso),
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.sys_hps_hps_io_hps_io_spim1_inst_SS0 (ltc_spi_csn),
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.sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx),
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.sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx),
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.sys_hps_hps_io_hps_io_i2c0_inst_SDA (adxl345_sda),
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.sys_hps_hps_io_hps_io_i2c0_inst_SCL (adxl345_scl),
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.sys_hps_hps_io_hps_io_i2c1_inst_SDA (ltc_i2c_sda),
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.sys_hps_hps_io_hps_io_i2c1_inst_SCL (ltc_i2c_scl),
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.sys_hps_hps_io_hps_io_gpio_inst_GPIO40 (ltc_i2c_spi_sel),
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.sys_hps_hps_io_hps_io_gpio_inst_GPIO53 (hps_gpio_led),
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.sys_hps_hps_io_hps_io_gpio_inst_GPIO54 (hps_gpio_pb),
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.sys_hps_hps_io_hps_io_gpio_inst_GPIO61 (adxl345_int),
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.sys_hps_i2c2_out_data(i2c2_sda_oe),
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.sys_hps_i2c2_sda(i2c2_sda),
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.sys_hps_i2c2_clk_clk(i2c2_scl_oe),
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.sys_hps_i2c2_scl_in_clk(i2c2_scl),
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.sys_hps_irq_in_irq (1'd0),
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.sys_hps_memory_mem_a (ddr3_a),
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.sys_hps_memory_mem_ba (ddr3_ba),
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.sys_hps_memory_mem_ck (ddr3_ck_p),
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.sys_hps_memory_mem_ck_n (ddr3_ck_n),
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.sys_hps_memory_mem_cke (ddr3_cke),
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.sys_hps_memory_mem_cs_n (ddr3_cs_n),
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.sys_hps_memory_mem_ras_n (ddr3_ras_n),
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.sys_hps_memory_mem_cas_n (ddr3_cas_n),
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.sys_hps_memory_mem_we_n (ddr3_we_n),
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.sys_hps_memory_mem_reset_n (ddr3_reset_n),
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.sys_hps_memory_mem_dq (ddr3_dq),
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.sys_hps_memory_mem_dqs (ddr3_dqs_p),
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.sys_hps_memory_mem_dqs_n (ddr3_dqs_n),
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.sys_hps_memory_mem_odt (ddr3_odt),
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.sys_hps_memory_mem_dm (ddr3_dm),
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.sys_hps_memory_oct_rzqin (ddr3_rzq),
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.sys_hps_spim0_txd (arduino_spi_mosi),
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.sys_hps_spim0_rxd (arduino_spi_miso),
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.sys_hps_spim0_ss_in_n (1'b1),
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.sys_hps_spim0_ssi_oe_n (),
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.sys_hps_spim0_ss_0_n (arduino_spi_csn[0]),
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.sys_hps_spim0_ss_1_n (arduino_spi_csn[1]),
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.sys_hps_spim0_ss_2_n (arduino_spi_csn[2]),
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.sys_hps_spim0_ss_3_n (arduino_spi_csn[3]),
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.sys_hps_spim0_clk_clk (arduino_spi_clk),
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.axi_hdmi_tx_0_hdmi_if_h_clk (hdmi_out_clk),
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.axi_hdmi_tx_0_hdmi_if_h16_hsync (),
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.axi_hdmi_tx_0_hdmi_if_h16_vsync (),
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.axi_hdmi_tx_0_hdmi_if_h16_data_e (),
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.axi_hdmi_tx_0_hdmi_if_h16_data (),
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.axi_hdmi_tx_0_hdmi_if_h16_es_data (),
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.axi_hdmi_tx_0_hdmi_if_h24_hsync (hdmi_hsync),
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.axi_hdmi_tx_0_hdmi_if_h24_vsync (hdmi_vsync),
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.axi_hdmi_tx_0_hdmi_if_h24_data_e (hdmi_data_e),
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.axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data),
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.axi_hdmi_tx_0_hdmi_if_h36_hsync (),
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.axi_hdmi_tx_0_hdmi_if_h36_vsync (),
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.axi_hdmi_tx_0_hdmi_if_h36_data_e (),
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.axi_hdmi_tx_0_hdmi_if_h36_data (),
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.axi_hdmi_tx_0_vdma_if_valid (hdmi_valid_s),
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.axi_hdmi_tx_0_vdma_if_data (hdmi_data_s),
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.axi_hdmi_tx_0_vdma_if_ready (hdmi_ready_s),
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.axi_hdmi_tx_0_if_vdma_fs_vdma_fs (hdmi_fs),
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.axi_hdmi_tx_0_if_vdma_fs_ret_vdma_fs_ret (hdmi_fs),
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.axi_dmac_0_if_m_axis_valid_valid (hdmi_valid_s),
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.axi_dmac_0_if_m_axis_data_data (hdmi_data_s),
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.axi_dmac_0_if_m_axis_ready_ready (hdmi_ready_s),
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.sys_hps_i2c3_scl_in_clk (i2c3_scl),
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.sys_hps_i2c3_clk_clk (i2c3_scl_oe),
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.sys_hps_i2c3_out_data (i2c3_sda_oe),
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.sys_hps_i2c3_sda (i2c3_sda),
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.sys_rst_reset_n (sys_resetn)
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);
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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