pluto_hdl_adi/library/jesd204
Iulia Moldovan 5c9b271f3a Fix error regarding hierarchy that Vivado misses
* Solution from here: https://support.xilinx.com/s/article/69320?language=en_US
 * Added in:
  * util_cdc
  * util_cic
  * jesd204_rx/tx
  * util_upack2
  * axi_jesd204_common: used in axi_jesd204_rx/tx
  * axi_jesd204_rx/tx
  * jesd_common

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
2023-08-01 18:12:40 +03:00
..
ad_ip_jesd204_tpl_adc Add/edit copyright and license for .v, .sv files 2023-07-11 15:17:41 +03:00
ad_ip_jesd204_tpl_common Add/edit copyright and license for .v, .sv files 2023-07-11 15:17:41 +03:00
ad_ip_jesd204_tpl_dac Add/edit copyright and license for .v, .sv files 2023-07-11 15:17:41 +03:00
axi_jesd204_common Fix error regarding hierarchy that Vivado misses 2023-08-01 18:12:40 +03:00
axi_jesd204_rx Fix error regarding hierarchy that Vivado misses 2023-08-01 18:12:40 +03:00
axi_jesd204_tx Fix error regarding hierarchy that Vivado misses 2023-08-01 18:12:40 +03:00
docs JESD204 Interface Framework : add logo 2021-09-16 16:49:52 +03:00
interfaces scripts: Merge adi_env.tcl into a single file 2022-08-08 13:52:54 +03:00
jesd204_common Fix error regarding hierarchy that Vivado misses 2023-08-01 18:12:40 +03:00
jesd204_rx Fix error regarding hierarchy that Vivado misses 2023-08-01 18:12:40 +03:00
jesd204_rx_static_config library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
jesd204_soft_pcs_rx library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
jesd204_soft_pcs_tx library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
jesd204_tx Fix error regarding hierarchy that Vivado misses 2023-08-01 18:12:40 +03:00
jesd204_tx_static_config library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
jesd204_versal_gt_adapter_rx library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
jesd204_versal_gt_adapter_tx library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
scripts library/jesd204: Update the script which computes the TPL width to be able to assign custom values 2022-08-25 12:35:42 +03:00
tb libraries: Update modules according to guideline 2022-06-28 18:06:56 +03:00
README.md jesd204: update README to reflect rev C 2020-06-23 13:52:35 +03:00

README.md

Analog Devices JESD204B HDL Support

Licensing

The ADI JESD204 Core is released under the following license, which is different than all other HDL cores in this repository.

Please read this, and understand the freedoms and responsibilities you have by using this source code/core.

The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.

This core is free software, you can use run, copy, study, change, ask questions about and improve this core. Distribution of source, or resulting binaries (including those inside an FPGA or ASIC) require you to release the source of the entire project (excluding the system libraries provide by the tools/compiler/FPGA vendor). These are the terms of the GNU General Public License version 2 as published by the Free Software Foundation.

This core is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License version 2 along with this source code, and binary. If not, see http://www.gnu.org/licenses/.

Commercial licenses (with commercial support) of this JESD204 core are also available under terms different than the General Public License. (e.g. they do not require you to accompany any image (FPGA or ASIC) using the JESD204 core with any corresponding source code.) For these alternate terms you must purchase a license from Analog Devices Technology Licensing Office. Users interested in such a license should contact jesd204-licensing@analog.com for more information. This commercial license is sub-licensable (if you purchase chips from Analog Devices, incorporate them into your PCB level product, and purchase a JESD204 license, end users of your product will also have a license to use this core in a commercial setting without releasing their source code).

In addition, we kindly ask you to acknowledge ADI in any program, application or publication in which you use this JESD204 HDL core. (You are not required to do so; it is up to your common sense to decide whether you want to comply with this request or not.) For general publications, we suggest referencing : “The design and implementation of the JESD204 HDL Core used in this project is copyright © 2016-2017, Analog Devices, Inc.”

Support

Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via https://ez.analog.com/community/fpga under the GPL license. If you would like deterministic support when using this core with an ADI component, please investigate a commercial license. Using a non-ADI JESD204 device with this core is possible under the GPL, but Analog Devices will not help with issues you may encounter.

Documenation