89 lines
3.4 KiB
Verilog
89 lines
3.4 KiB
Verilog
//
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// The ADI JESD204 Core is released under the following license, which is
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// different than all other HDL cores in this repository.
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//
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// Please read this, and understand the freedoms and responsibilities you have
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// by using this source code/core.
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//
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// The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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//
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// This core is free software, you can use run, copy, study, change, ask
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// questions about and improve this core. Distribution of source, or resulting
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// binaries (including those inside an FPGA or ASIC) require you to release the
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// source of the entire project (excluding the system libraries provide by the
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// tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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// License version 2 as published by the Free Software Foundation.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License version 2
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// along with this source code, and binary. If not, see
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// <http://www.gnu.org/licenses/>.
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//
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// Commercial licenses (with commercial support) of this JESD204 core are also
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// available under terms different than the General Public License. (e.g. they
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// do not require you to accompany any image (FPGA or ASIC) using the JESD204
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// core with any corresponding source code.) For these alternate terms you must
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// purchase a license from Analog Devices Technology Licensing Office. Users
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// interested in such a license should contact jesd204-licensing@analog.com for
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// more information. This commercial license is sub-licensable (if you purchase
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// chips from Analog Devices, incorporate them into your PCB level product, and
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// purchase a JESD204 license, end users of your product will also have a
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// license to use this core in a commercial setting without releasing their
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// source code).
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//
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// In addition, we kindly ask you to acknowledge ADI in any program, application
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// or publication in which you use this JESD204 HDL core. (You are not required
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// to do so; it is up to your common sense to decide whether you want to comply
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// with this request or not.) For general publications, we suggest referencing :
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// “The design and implementation of the JESD204 HDL Core used in this project
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// is copyright © 2016-2017, Analog Devices, Inc.”
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//
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`timescale 1ns/100ps
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module jesd204_crc12 #(
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parameter WIDTH = 64
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) (
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input clk,
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input reset,
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input init,
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input [WIDTH-1:0] data_in,
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output [11:0] crc12
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);
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reg [11:0] state = 12'b0;
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wire [WIDTH-1:0] feedback;
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wire [WIDTH-1+12:0] full_state;
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assign full_state = {init ? 12'h0 : state, feedback};
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assign feedback = full_state[WIDTH-1+12:12] ^
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full_state[WIDTH-1:11] ^
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full_state[WIDTH-1:10] ^
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full_state[WIDTH-1:9] ^
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full_state[WIDTH-1:4] ^
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full_state[WIDTH-1:3] ^
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data_in;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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state <= 12'b0;
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end else begin
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state <= full_state[11:0] ^
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{full_state[10:0],1'b0} ^
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{full_state[9:0],2'b0} ^
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{full_state[8:0],3'b0} ^
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{full_state[3:0],8'b0} ^
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{full_state[2:0],9'b0};
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end
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end
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assign crc12 = state;
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endmodule
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