AndreiGrozav 568f2e180f ad_mul.v: Add parameters for A and B input widths ... The out width will be A + B. This change is backward compatible and it applies to both Altera and Xilinx.		2018-07-18 18:19:30 +03:00
..
ad_data_clk.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
ad_data_in.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
ad_data_out.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
ad_dcfilter.v	Move Xilinx specific DC filter implementation to library/xilinx/common/	2018-04-11 15:09:54 +03:00
ad_iobuf.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
ad_mmcm_drp.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
ad_mul.v	ad_mul.v: Add parameters for A and B input widths	2018-07-18 18:19:30 +03:00
ad_rst_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00
ad_serdes_clk.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
ad_serdes_in.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
ad_serdes_out.v	license: Fix a spelling mistake	2018-04-11 15:09:54 +03:00
up_clock_mon_constr.xdc	up_clock_com: Fix the false path definitions for CDCs	2018-04-11 15:09:54 +03:00
up_xfer_cntrl_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00
up_xfer_status_constr.xdc	restructure: Move xilinx specific constraints to /library/xilinx/common/	2017-03-30 16:16:02 +03:00