419 lines
13 KiB
Verilog
419 lines
13 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adcfifo_wr #(
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parameter AXI_DATA_WIDTH = 512,
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parameter AXI_SIZE = 2,
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parameter AXI_LENGTH = 16,
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parameter AXI_ADDRESS = 32'h00000000,
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parameter AXI_ADDRESS_LIMIT = 32'h00000000) (
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// request and synchronization
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input dma_xfer_req,
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// read interface
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output reg axi_rd_req,
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output reg [ 31:0] axi_rd_addr,
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// fifo interface
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input adc_rst,
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input adc_clk,
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input adc_wr,
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input [AXI_DATA_WIDTH-1:0] adc_wdata,
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// axi interface
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input axi_clk,
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input axi_resetn,
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output reg axi_awvalid,
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output [ 3:0] axi_awid,
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output [ 1:0] axi_awburst,
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output axi_awlock,
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output [ 3:0] axi_awcache,
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output [ 2:0] axi_awprot,
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output [ 3:0] axi_awqos,
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output [ 3:0] axi_awuser,
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output [ 7:0] axi_awlen,
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output [ 2:0] axi_awsize,
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output reg [ 31:0] axi_awaddr,
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input axi_awready,
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output axi_wvalid,
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output [AXI_DATA_WIDTH-1:0] axi_wdata,
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output [AXI_BYTE_WIDTH-1:0] axi_wstrb,
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output axi_wlast,
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output [ 3:0] axi_wuser,
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input axi_wready,
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input axi_bvalid,
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input [ 3:0] axi_bid,
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input [ 1:0] axi_bresp,
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input [ 3:0] axi_buser,
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output axi_bready,
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// axi status
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output reg axi_dwovf,
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output reg axi_dwunf,
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output reg axi_werror);
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localparam AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
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localparam AXI_AWINCR = AXI_LENGTH * AXI_BYTE_WIDTH;
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localparam BUF_THRESHOLD_LO = 8'd6;
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localparam BUF_THRESHOLD_HI = 8'd250;
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// internal registers
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reg [ 2:0] adc_xfer_req_m = 'd0;
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reg adc_xfer_init = 'd0;
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reg adc_xfer_limit = 'd0;
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reg adc_xfer_enable = 'd0;
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reg [ 31:0] adc_xfer_addr = 'd0;
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reg [ 7:0] adc_waddr = 'd0;
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reg [ 7:0] adc_waddr_g = 'd0;
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reg adc_rel_enable = 'd0;
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reg adc_rel_toggle = 'd0;
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reg [ 7:0] adc_rel_waddr = 'd0;
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reg [ 2:0] axi_rel_toggle_m = 'd0;
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reg [ 7:0] axi_rel_waddr = 'd0;
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reg [ 7:0] axi_waddr_m1 = 'd0;
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reg [ 7:0] axi_waddr_m2 = 'd0;
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reg [ 7:0] axi_waddr = 'd0;
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reg [ 7:0] axi_addr_diff = 'd0;
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reg axi_almost_full = 'd0;
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reg axi_almost_empty = 'd0;
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reg [ 2:0] axi_xfer_req_m = 'd0;
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reg axi_xfer_init = 'd0;
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reg [ 7:0] axi_raddr = 'd0;
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reg axi_rd = 'd0;
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reg axi_rlast = 'd0;
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reg axi_rd_d = 'd0;
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reg axi_rlast_d = 'd0;
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reg [AXI_DATA_WIDTH-1:0] axi_rdata_d = 'd0;
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reg axi_reset = 'd0;
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// internal signals
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wire axi_rel_toggle_s;
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wire [ 8:0] axi_addr_diff_s;
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wire axi_wready_s;
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wire axi_rd_s;
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wire axi_req_s;
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wire axi_rlast_s;
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wire [AXI_DATA_WIDTH-1:0] axi_rdata_s;
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// binary to grey conversion
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function [7:0] b2g;
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input [7:0] b;
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reg [7:0] g;
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begin
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g[7] = b[7];
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g[6] = b[7] ^ b[6];
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g[5] = b[6] ^ b[5];
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g[4] = b[5] ^ b[4];
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g[3] = b[4] ^ b[3];
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g[2] = b[3] ^ b[2];
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g[1] = b[2] ^ b[1];
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g[0] = b[1] ^ b[0];
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b2g = g;
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end
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endfunction
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// grey to binary conversion
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function [7:0] g2b;
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input [7:0] g;
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reg [7:0] b;
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begin
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b[7] = g[7];
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b[6] = b[7] ^ g[6];
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b[5] = b[6] ^ g[5];
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b[4] = b[5] ^ g[4];
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b[3] = b[4] ^ g[3];
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b[2] = b[3] ^ g[2];
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b[1] = b[2] ^ g[1];
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b[0] = b[1] ^ g[0];
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g2b = b;
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end
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endfunction
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// fifo interface
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always @(posedge adc_clk) begin
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if (adc_rst == 1'b1) begin
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adc_waddr <= 'd0;
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adc_waddr_g <= 'd0;
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adc_xfer_req_m <= 'd0;
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adc_xfer_init <= 'd0;
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adc_xfer_limit <= 'd0;
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adc_xfer_enable <= 'd0;
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adc_xfer_addr <= 'd0;
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adc_rel_enable <= 'd0;
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adc_rel_toggle <= 'd0;
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adc_rel_waddr <= 'd0;
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end else begin
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if ((adc_wr == 1'b1) && (adc_xfer_enable == 1'b1)) begin
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adc_waddr <= adc_waddr + 1'b1;
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end
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adc_waddr_g <= b2g(adc_waddr);
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adc_xfer_req_m <= {adc_xfer_req_m[1:0], dma_xfer_req};
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adc_xfer_init <= adc_xfer_req_m[1] & ~adc_xfer_req_m[2];
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if (adc_xfer_init == 1'b1) begin
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adc_xfer_limit <= 1'd1;
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end else if ((adc_xfer_addr >= AXI_ADDRESS_LIMIT) || (adc_xfer_enable == 1'b0)) begin
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adc_xfer_limit <= 1'd0;
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end
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if (adc_xfer_init == 1'b1) begin
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adc_xfer_enable <= 1'b1;
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adc_xfer_addr <= AXI_ADDRESS;
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end else if ((adc_waddr[1:0] == 2'h3) && (adc_wr == 1'b1)) begin
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adc_xfer_enable <= adc_xfer_req_m[2] & adc_xfer_limit;
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adc_xfer_addr <= adc_xfer_addr + AXI_AWINCR;
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end
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if (adc_waddr[1:0] == 2'h3) begin
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adc_rel_enable <= adc_wr;
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end else begin
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adc_rel_enable <= 1'd0;
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end
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if (adc_rel_enable == 1'b1) begin
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adc_rel_toggle <= ~adc_rel_toggle;
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adc_rel_waddr <= adc_waddr;
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end
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end
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end
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// fifo signals on axi side
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assign axi_rel_toggle_s = axi_rel_toggle_m[2] ^ axi_rel_toggle_m[1];
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_rel_toggle_m <= 'd0;
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axi_rel_waddr <= 'd0;
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axi_waddr_m1 <= 'd0;
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axi_waddr_m2 <= 'd0;
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axi_waddr <= 'd0;
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end else begin
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axi_rel_toggle_m <= {axi_rel_toggle_m[1:0], adc_rel_toggle};
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if (axi_rel_toggle_s == 1'b1) begin
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axi_rel_waddr <= adc_rel_waddr;
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end
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axi_waddr_m1 <= adc_waddr_g;
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axi_waddr_m2 <= axi_waddr_m1;
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axi_waddr <= g2b(axi_waddr_m2);
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end
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end
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// overflow (no underflow possible)
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assign axi_addr_diff_s = {1'b1, axi_waddr} - axi_raddr;
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_addr_diff <= 'd0;
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axi_almost_full <= 'd0;
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axi_dwunf <= 'd0;
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axi_almost_empty <= 'd0;
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axi_dwovf <= 'd0;
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end else begin
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axi_addr_diff <= axi_addr_diff_s[7:0];
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if (axi_addr_diff > BUF_THRESHOLD_HI) begin
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axi_almost_full <= 1'b1;
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axi_dwunf <= axi_almost_empty;
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end else begin
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axi_almost_full <= 1'b0;
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axi_dwunf <= 1'b0;
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end
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if (axi_addr_diff < BUF_THRESHOLD_LO) begin
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axi_almost_empty <= 1'b1;
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axi_dwovf <= axi_almost_full;
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end else begin
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axi_almost_empty <= 1'b0;
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axi_dwovf <= 1'b0;
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end
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end
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end
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// transfer request is required to keep things in sync
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_xfer_req_m <= 'd0;
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axi_xfer_init <= 'd0;
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end else begin
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axi_xfer_req_m <= {axi_xfer_req_m[1:0], dma_xfer_req};
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axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
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end
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end
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// read is initiated if xfer enabled
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assign axi_wready_s = ~axi_wvalid | axi_wready;
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assign axi_rd_s = (axi_rel_waddr == axi_raddr) ? 1'b0 : axi_wready_s;
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assign axi_req_s = (axi_raddr[1:0] == 2'h0) ? axi_rd_s : 1'b0;
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assign axi_rlast_s = (axi_raddr[1:0] == 2'h3) ? axi_rd_s : 1'b0;
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_raddr <= 'd0;
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axi_rd <= 'd0;
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axi_rlast <= 'd0;
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axi_rd_d <= 'd0;
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axi_rlast_d <= 'd0;
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axi_rdata_d <= 'd0;
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end else begin
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if (axi_rd_s == 1'b1) begin
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axi_raddr <= axi_raddr + 1'b1;
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end
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axi_rd <= axi_rd_s;
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axi_rlast <= axi_rlast_s;
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axi_rd_d <= axi_rd;
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axi_rlast_d <= axi_rlast;
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axi_rdata_d <= axi_rdata_s;
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end
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end
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// send read request for every burst about to be completed
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_rd_req <= 'd0;
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axi_rd_addr <= 'd0;
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end else begin
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axi_rd_req <= axi_rlast_s;
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if (axi_xfer_init == 1'b1) begin
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axi_rd_addr <= AXI_ADDRESS;
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end else if (axi_rd_req == 1'b1) begin
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axi_rd_addr <= axi_rd_addr + AXI_AWINCR;
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end
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end
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end
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// address channel
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assign axi_awid = 4'b0000;
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assign axi_awburst = 2'b01;
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assign axi_awlock = 1'b0;
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assign axi_awcache = 4'b0010;
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assign axi_awprot = 3'b000;
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assign axi_awqos = 4'b0000;
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assign axi_awuser = 4'b0001;
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assign axi_awlen = AXI_LENGTH - 1;
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assign axi_awsize = AXI_SIZE;
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_awvalid <= 'd0;
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axi_awaddr <= 'd0;
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end else begin
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if (axi_awvalid == 1'b1) begin
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if (axi_awready == 1'b1) begin
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axi_awvalid <= 1'b0;
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end
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end else begin
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if (axi_req_s == 1'b1) begin
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axi_awvalid <= 1'b1;
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end
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end
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if (axi_xfer_init == 1'b1) begin
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axi_awaddr <= AXI_ADDRESS;
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end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
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axi_awaddr <= axi_awaddr + AXI_AWINCR;
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end
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end
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end
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// write channel
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assign axi_wstrb = {AXI_BYTE_WIDTH{1'b1}};
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assign axi_wuser = 4'b0000;
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// response channel
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assign axi_bready = 1'b1;
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_werror <= 'd0;
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end else begin
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axi_werror <= axi_bvalid & axi_bready & axi_bresp[1];
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end
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end
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// fifo needs a reset
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always @(posedge axi_clk or negedge axi_resetn) begin
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if (axi_resetn == 1'b0) begin
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axi_reset <= 1'b1;
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end else begin
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axi_reset <= 1'b0;
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end
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end
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// interface handler
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ad_axis_inf_rx #(.DATA_WIDTH(AXI_DATA_WIDTH)) i_axis_inf (
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.clk (axi_clk),
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.rst (axi_reset),
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.valid (axi_rd_d),
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.last (axi_rlast_d),
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.data (axi_rdata_d),
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.inf_valid (axi_wvalid),
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.inf_last (axi_wlast),
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.inf_data (axi_wdata),
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.inf_ready (axi_wready));
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// buffer
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ad_mem #(.DATA_WIDTH(AXI_DATA_WIDTH), .ADDRESS_WIDTH(8)) i_mem (
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.clka (adc_clk),
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.wea (adc_wr),
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.addra (adc_waddr),
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.dina (adc_wdata),
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.clkb (axi_clk),
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.reb (1'b1),
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.addrb (axi_raddr),
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.doutb (axi_rdata_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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