427 lines
14 KiB
Verilog
427 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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sys_clk,
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sys_resetn,
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// ddr3
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ddr3_a,
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ddr3_ba,
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ddr3_clk_p,
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ddr3_clk_n,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_ras_n,
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ddr3_cas_n,
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ddr3_we_n,
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ddr3_reset_n,
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ddr3_dq,
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ddr3_dqs_p,
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ddr3_dqs_n,
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ddr3_odt,
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ddr3_rzq,
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// ethernet
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eth_rx_clk,
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eth_rx_data,
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eth_rx_cntrl,
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eth_tx_clk_out,
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eth_tx_data,
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eth_tx_cntrl,
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eth_mdc,
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eth_mdio_i,
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eth_mdio_o,
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eth_mdio_t,
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eth_phy_resetn,
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// board gpio
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led_grn,
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led_red,
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push_buttons,
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dip_switches,
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// lane interface
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ref_clk,
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rx_data,
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rx_sync,
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rx_sysref,
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// spi
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spi_csn,
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spi_clk,
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spi_sdio);
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// clock and resets
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input sys_clk;
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input sys_resetn;
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// ddr3
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output [ 13:0] ddr3_a;
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output [ 2:0] ddr3_ba;
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output ddr3_clk_p;
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output ddr3_clk_n;
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output ddr3_cke;
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output ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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output ddr3_ras_n;
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output ddr3_cas_n;
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output ddr3_we_n;
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output ddr3_reset_n;
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inout [ 63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_p;
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inout [ 7:0] ddr3_dqs_n;
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output ddr3_odt;
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input ddr3_rzq;
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// ethernet
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input eth_rx_clk;
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input [ 3:0] eth_rx_data;
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input eth_rx_cntrl;
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output eth_tx_clk_out;
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output [ 3:0] eth_tx_data;
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output eth_tx_cntrl;
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output eth_mdc;
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input eth_mdio_i;
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output eth_mdio_o;
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output eth_mdio_t;
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output eth_phy_resetn;
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// board gpio
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output [ 7:0] led_grn;
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output [ 7:0] led_red;
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input [ 2:0] push_buttons;
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input [ 7:0] dip_switches;
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// lane interface
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input ref_clk;
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input [ 3:0] rx_data;
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output rx_sync;
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output rx_sysref;
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// spi
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output spi_csn;
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output spi_clk;
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inout spi_sdio;
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// internal registers
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reg rx_sysref_m1 = 'd0;
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reg rx_sysref_m2 = 'd0;
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reg rx_sysref_m3 = 'd0;
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reg rx_sysref = 'd0;
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reg dma0_wr = 'd0;
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reg [ 63:0] dma0_wdata = 'd0;
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reg dma1_wr = 'd0;
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reg [ 63:0] dma1_wdata = 'd0;
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// internal clocks and resets
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wire sys_125m_clk;
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wire sys_25m_clk;
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wire sys_2m5_clk;
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wire eth_tx_clk;
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wire rx_clk;
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wire adc0_clk;
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wire adc1_clk;
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// internal signals
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wire sys_pll_locked_s;
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wire eth_tx_reset_s;
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wire eth_tx_mode_1g_s;
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wire eth_tx_mode_10m_100m_n_s;
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wire spi_mosi;
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wire spi_miso;
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wire adc0_enable_a_s;
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wire [ 31:0] adc0_data_a_s;
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wire adc0_enable_b_s;
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wire [ 31:0] adc0_data_b_s;
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wire adc0_dovf_s;
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wire adc1_enable_a_s;
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wire [ 31:0] adc1_data_a_s;
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wire adc1_enable_b_s;
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wire [ 31:0] adc1_data_b_s;
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wire adc1_dovf_s;
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wire [ 3:0] rx_ip_sof_s;
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wire [127:0] rx_ip_data_s;
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wire [127:0] rx_data_s;
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wire rx_sw_rstn_s;
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wire rx_sysref_s;
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wire rx_err_s;
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wire rx_ready_s;
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wire [ 3:0] rx_rst_state_s;
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wire rx_lane_aligned_s;
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wire [ 3:0] rx_analog_reset_s;
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wire [ 3:0] rx_digital_reset_s;
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wire [ 3:0] rx_cdr_locked_s;
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wire [ 3:0] rx_cal_busy_s;
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wire rx_pll_locked_s;
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wire [ 15:0] rx_xcvr_status_s;
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reg [ 3:0] phy_rst_cnt = 0;
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reg phy_rst_reg = 0;
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// ethernet transmit clock
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assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
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(eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
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assign eth_phy_resetn = phy_rst_reg;
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always@ (posedge eth_mdc) begin
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phy_rst_cnt <= phy_rst_cnt +1;
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if (phy_rst_cnt == 4'h0) begin
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phy_rst_reg <= sys_pll_locked_s;
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end
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end
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altddio_out #(.width(1)) i_eth_tx_clk_out (
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.aset (1'b0),
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.sset (1'b0),
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.sclr (1'b0),
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.oe (1'b1),
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.oe_out (),
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.datain_h (1'b1),
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.datain_l (1'b0),
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.outclocken (1'b1),
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.aclr (eth_tx_reset_s),
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.outclock (eth_tx_clk),
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.dataout (eth_tx_clk_out));
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assign eth_tx_reset_s = ~sys_pll_locked_s;
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always @(posedge rx_clk) begin
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rx_sysref_m1 <= rx_sysref_s;
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rx_sysref_m2 <= rx_sysref_m1;
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rx_sysref_m3 <= rx_sysref_m2;
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rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
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end
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always @(posedge rx_clk) begin
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dma0_wr <= adc0_enable_a_s & adc0_enable_b_s;
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dma0_wdata <= { adc0_data_b_s[31:16],
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adc0_data_a_s[31:16],
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adc0_data_b_s[15: 0],
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adc0_data_a_s[15: 0]};
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dma1_wr <= adc1_enable_a_s & adc1_enable_b_s;
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dma1_wdata <= { adc1_data_b_s[31:16],
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adc1_data_a_s[31:16],
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adc1_data_b_s[15: 0],
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adc1_data_a_s[15: 0]};
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end
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sld_signaltap #(
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.sld_advanced_trigger_entity ("basic,1,"),
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.sld_data_bits (130),
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.sld_data_bit_cntr_bits (8),
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.sld_enable_advanced_trigger (0),
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.sld_mem_address_bits (10),
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.sld_node_crc_bits (32),
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.sld_node_crc_hiword (10311),
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.sld_node_crc_loword (14297),
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.sld_node_info (1076736),
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.sld_ram_block_type ("AUTO"),
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.sld_sample_depth (1024),
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.sld_storage_qualifier_gap_record (0),
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.sld_storage_qualifier_mode ("OFF"),
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.sld_trigger_bits (2),
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.sld_trigger_in_enabled (0),
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.sld_trigger_level (1),
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.sld_trigger_level_pipeline (1))
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i_signaltap (
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.acq_clk (rx_clk),
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.acq_data_in ({ rx_sysref,
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rx_sync,
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adc1_data_b_s,
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adc1_data_a_s,
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adc0_data_b_s,
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adc0_data_a_s}),
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.acq_trigger_in ({rx_sysref, rx_sync}));
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genvar n;
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generate
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for (n = 0; n < 4; n = n + 1) begin: g_align_1
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ad_jesd_align i_jesd_align (
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.rx_clk (rx_clk),
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.rx_sof (rx_ip_sof_s),
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.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
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.rx_data (rx_data_s[n*32+31:n*32]));
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end
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endgenerate
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assign rx_xcvr_status_s[15:15] = 1'd0;
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assign rx_xcvr_status_s[14:14] = rx_sync;
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assign rx_xcvr_status_s[13:13] = rx_ready_s;
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assign rx_xcvr_status_s[12:12] = rx_pll_locked_s;
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assign rx_xcvr_status_s[11: 8] = rx_rst_state_s;
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assign rx_xcvr_status_s[ 7: 4] = rx_cdr_locked_s;
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assign rx_xcvr_status_s[ 3: 0] = rx_cal_busy_s;
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ad_xcvr_rx_rst #(.NUM_OF_LANES (4)) i_xcvr_rx_rst (
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.rx_clk (rx_clk),
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.rx_rstn (sys_resetn),
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.rx_sw_rstn (rx_sw_rstn_s),
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.rx_pll_locked (rx_pll_locked_s),
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.rx_cal_busy (rx_cal_busy_s),
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.rx_cdr_locked (rx_cdr_locked_s),
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.rx_analog_reset (rx_analog_reset_s),
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.rx_digital_reset (rx_digital_reset_s),
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.rx_ready (rx_ready_s),
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.rx_rst_state (rx_rst_state_s));
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fmcjesdadc1_spi i_fmcjesdadc1_spi (
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.spi_csn (spi_csn),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio));
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system_bd i_system_bd (
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.sys_clk_clk (sys_clk),
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.sys_reset_reset_n (sys_resetn),
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.sys_125m_clk_clk (sys_125m_clk),
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.sys_25m_clk_clk (sys_25m_clk),
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.sys_2m5_clk_clk (sys_2m5_clk),
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.sys_ddr3_phy_mem_a (ddr3_a),
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.sys_ddr3_phy_mem_ba (ddr3_ba),
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.sys_ddr3_phy_mem_ck (ddr3_clk_p),
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.sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
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.sys_ddr3_phy_mem_cke (ddr3_cke),
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.sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
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.sys_ddr3_phy_mem_dm (ddr3_dm),
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.sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
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.sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
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.sys_ddr3_phy_mem_we_n (ddr3_we_n),
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.sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
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.sys_ddr3_phy_mem_dq (ddr3_dq),
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.sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
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.sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
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.sys_ddr3_phy_mem_odt (ddr3_odt),
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.sys_ddr3_oct_rzqin (ddr3_rzq),
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.sys_ethernet_tx_clk_clk (eth_tx_clk),
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.sys_ethernet_rx_clk_clk (eth_rx_clk),
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.sys_ethernet_status_set_10 (),
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.sys_ethernet_status_set_1000 (),
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.sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
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.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
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.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
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.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
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.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
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.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
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.sys_ethernet_mdio_mdc (eth_mdc),
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.sys_ethernet_mdio_mdio_in (eth_mdio_i),
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.sys_ethernet_mdio_mdio_out (eth_mdio_o),
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.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
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.sys_gpio_in_port ({rx_xcvr_status_s, 5'd0, push_buttons, dip_switches}),
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.sys_gpio_out_port ({14'd0, rx_sw_rstn_s, rx_sysref_s, led_grn, led_red}),
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.sys_spi_MISO (spi_miso),
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.sys_spi_MOSI (spi_mosi),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn),
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.axi_ad9250_0_xcvr_clk_clk (rx_clk),
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.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
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.axi_ad9250_0_adc_clock_clk (adc0_clk),
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.axi_ad9250_0_adc_dma_if_adc_valid_a (),
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.axi_ad9250_0_adc_dma_if_adc_enable_a (adc0_enable_a_s),
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.axi_ad9250_0_adc_dma_if_adc_data_a (adc0_data_a_s),
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.axi_ad9250_0_adc_dma_if_adc_valid_b (),
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.axi_ad9250_0_adc_dma_if_adc_enable_b (adc0_enable_b_s),
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.axi_ad9250_0_adc_dma_if_adc_data_b (adc0_data_b_s),
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.axi_ad9250_0_adc_dma_if_adc_dovf (adc0_dovf_s),
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.axi_ad9250_0_adc_dma_if_adc_dunf (1'b0),
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.axi_dmac_0_fifo_wr_clock_clk (adc0_clk),
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.axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s),
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.axi_dmac_0_fifo_wr_if_wren (dma0_wr),
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.axi_dmac_0_fifo_wr_if_data (dma0_wdata),
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.axi_dmac_0_fifo_wr_if_sync (1'b1),
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.axi_ad9250_1_xcvr_clk_clk (rx_clk),
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.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
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.axi_ad9250_1_adc_clock_clk (adc1_clk),
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.axi_ad9250_1_adc_dma_if_adc_valid_a (),
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.axi_ad9250_1_adc_dma_if_adc_enable_a (adc1_enable_a_s),
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.axi_ad9250_1_adc_dma_if_adc_data_a (adc1_data_a_s),
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.axi_ad9250_1_adc_dma_if_adc_valid_b (),
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.axi_ad9250_1_adc_dma_if_adc_enable_b (adc1_enable_b_s),
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.axi_ad9250_1_adc_dma_if_adc_data_b (adc1_data_b_s),
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.axi_ad9250_1_adc_dma_if_adc_dovf (adc1_dovf_s),
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.axi_ad9250_1_adc_dma_if_adc_dunf (1'b0),
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.axi_dmac_1_fifo_wr_clock_clk (adc1_clk),
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.axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s),
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.axi_dmac_1_fifo_wr_if_wren (dma1_wr),
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.axi_dmac_1_fifo_wr_if_data (dma1_wdata),
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.axi_dmac_1_fifo_wr_if_sync (1'b1),
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.sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
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.sys_jesd204b_s1_rx_link_valid (),
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.sys_jesd204b_s1_rx_link_ready (1'b1),
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.sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
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.sys_jesd204b_s1_sysref_export (rx_sysref),
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.sys_jesd204b_s1_rx_ferr_export (rx_err_s),
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.sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
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.sys_jesd204b_s1_sync_n_export (rx_sync),
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.sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
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.sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
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.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
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.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
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.sys_jesd204b_s1_locked_export (rx_cdr_locked_s),
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.sys_jesd204b_s1_rx_cal_busy_export (rx_cal_busy_s),
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.sys_jesd204b_s1_ref_clk_clk (ref_clk),
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.sys_jesd204b_s1_rx_clk_clk (rx_clk),
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.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
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.sys_pll_locked_export (sys_pll_locked_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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