75 lines
3.1 KiB
Tcl
75 lines
3.1 KiB
Tcl
###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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## ADC FIFO depth in samples per converter
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set adc_fifo_samples_per_converter [expr 64*1024]
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## DAC FIFO depth in samples per converter
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set dac_fifo_samples_per_converter [expr 64*1024]
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source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
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source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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sysid_gen_sys_init_file
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# Parameters for 15.5Gpbs lane rate
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ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 31
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ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 31
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x1fa
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x23
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x2
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2
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ad_ip_parameter util_mxfe_xcvr CONFIG.A_TXDIFFCTRL 0xc
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG0 0x3
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN2 0x265
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x1A
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x1A
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x1A
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12
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ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x6868
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ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 1
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x4
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x0
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ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG 0x0
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ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 3
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_ip_parameter util_mxfe_xcvr CONFIG.POR_CFG 0x0
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x333c
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x45
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20
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ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0xF00
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP 0xFF
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP_G3 0xF
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x2FF
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# Overwrite parameter for lower lane rates which use CPLL
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if {$ad_project_params(RX_LANE_RATE) < 12} {
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ad_ip_parameter util_mxfe_xcvr CONFIG.RX_WIDEMODE_CDR 0x0
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x200
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0xFD
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x12
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12
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}
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