131 lines
5.2 KiB
Tcl
131 lines
5.2 KiB
Tcl
###############################################################################
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## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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## ADC FIFO depth in samples per converter
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set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024]
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## DAC FIFO depth in samples per converter
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set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024]
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source $ad_hdl_dir/projects/common/vcu118/vcu118_system_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
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source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
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source ../common/ad_quadmxfe1_ebz_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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# Set SPI clock to 100/16 = 6.25 MHz
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ad_ip_parameter axi_spi CONFIG.C_SCK_RATIO 16
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set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt;
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#system ID
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
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set sys_cstring "sys rom custom string placeholder"
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sysid_gen_sys_init_file $sys_cstring
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if {$ad_project_params(JESD_MODE) == "8B10B"} {
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# Parameters for 10Gpbs lane rate
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ad_ip_parameter util_mxfe_xcvr CONFIG.RX_CLK25_DIV 20
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ad_ip_parameter util_mxfe_xcvr CONFIG.TX_CLK25_DIV 20
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG0 0x3fe
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG1 0x29
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_CFG2 0x203
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ad_ip_parameter util_mxfe_xcvr CONFIG.CPLL_FBDIV 2
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ad_ip_parameter util_mxfe_xcvr CONFIG.A_TXDIFFCTRL 0xc
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG0 0x3
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN2 0x265
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG2_GEN4 0x164
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3 0x12
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN2 0x12
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN3 0x12
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXCDR_CFG3_GEN4 0x12
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ad_ip_parameter util_mxfe_xcvr CONFIG.CH_HSPMUX 0x2020
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ad_ip_parameter util_mxfe_xcvr CONFIG.PREIQ_FREQ_BST 0
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG0 0x1002
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ad_ip_parameter util_mxfe_xcvr CONFIG.RXPI_CFG1 0x15
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ad_ip_parameter util_mxfe_xcvr CONFIG.TXPI_CFG 0x54
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ad_ip_parameter util_mxfe_xcvr CONFIG.TX_PI_BIASSET 0
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_ip_parameter util_mxfe_xcvr CONFIG.POR_CFG 0x0
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG0 0x331c
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG2 0xFC1
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG2_G3 0xFC1
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CFG4 0x1
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_FBDIV 20
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ad_ip_parameter util_mxfe_xcvr CONFIG.PPF0_CFG 0x400
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP 0xFF
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_CP_G3 0xF
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ad_ip_parameter util_mxfe_xcvr CONFIG.QPLL_LPF 0x27F
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} else {
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ad_ip_instance util_ds_buf sys_cpu_clk_BUFGCE
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ad_ip_parameter sys_cpu_clk_BUFGCE CONFIG.C_BUF_TYPE {BUFGCE_DIV}
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ad_ip_parameter sys_cpu_clk_BUFGCE CONFIG.C_BUFGCE_DIV 2
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ad_connect sys_cpu_clk_BUFGCE/BUFGCE_CE VCC
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ad_connect sys_cpu_clk_BUFGCE/BUFGCE_CLR GND
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ad_connect sys_cpu_clk_BUFGCE/BUFGCE_I $sys_cpu_clk
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ad_connect sys_cpu_clk_BUFGCE/BUFGCE_O jesd204_phy_121_122/drpclk
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ad_connect sys_cpu_clk_BUFGCE/BUFGCE_O jesd204_phy_125_126/drpclk
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}
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# Second SPI controller
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create_bd_port -dir O -from 7 -to 0 spi_2_csn_o
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create_bd_port -dir I -from 7 -to 0 spi_2_csn_i
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create_bd_port -dir I spi_2_clk_i
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create_bd_port -dir O spi_2_clk_o
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create_bd_port -dir I spi_2_sdo_i
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create_bd_port -dir O spi_2_sdo_o
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create_bd_port -dir I spi_2_sdi_i
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ad_ip_instance axi_quad_spi axi_spi_2
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ad_ip_parameter axi_spi_2 CONFIG.C_USE_STARTUP 0
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ad_ip_parameter axi_spi_2 CONFIG.C_NUM_SS_BITS 8
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ad_ip_parameter axi_spi_2 CONFIG.C_SCK_RATIO 8
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ad_connect spi_2_csn_i axi_spi_2/ss_i
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ad_connect spi_2_csn_o axi_spi_2/ss_o
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ad_connect spi_2_clk_i axi_spi_2/sck_i
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ad_connect spi_2_clk_o axi_spi_2/sck_o
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ad_connect spi_2_sdo_i axi_spi_2/io0_i
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ad_connect spi_2_sdo_o axi_spi_2/io0_o
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ad_connect spi_2_sdi_i axi_spi_2/io1_i
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ad_connect sys_cpu_clk axi_spi_2/ext_spi_clk
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ad_cpu_interrupt ps-15 mb-7 axi_spi_2/ip2intc_irpt
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ad_cpu_interconnect 0x44A80000 axi_spi_2
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# Third SPI controller
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create_bd_port -dir O -from 7 -to 0 spi_3_csn_o
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create_bd_port -dir I -from 7 -to 0 spi_3_csn_i
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create_bd_port -dir I spi_3_clk_i
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create_bd_port -dir O spi_3_clk_o
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create_bd_port -dir I spi_3_sdo_i
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create_bd_port -dir O spi_3_sdo_o
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create_bd_port -dir I spi_3_sdi_i
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ad_ip_instance axi_quad_spi axi_spi_3
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ad_ip_parameter axi_spi_3 CONFIG.C_USE_STARTUP 0
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ad_ip_parameter axi_spi_3 CONFIG.C_NUM_SS_BITS 8
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ad_ip_parameter axi_spi_3 CONFIG.C_SCK_RATIO 16
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ad_ip_parameter axi_spi_3 CONFIG.Multiples16 16
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ad_connect spi_3_csn_i axi_spi_3/ss_i
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ad_connect spi_3_csn_o axi_spi_3/ss_o
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ad_connect spi_3_clk_i axi_spi_3/sck_i
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ad_connect spi_3_clk_o axi_spi_3/sck_o
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ad_connect spi_3_sdo_i axi_spi_3/io0_i
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ad_connect spi_3_sdo_o axi_spi_3/io0_o
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ad_connect spi_3_sdi_i axi_spi_3/io1_i
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ad_connect sys_cpu_clk axi_spi_3/ext_spi_clk
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ad_cpu_interrupt ps-15 mb-6 axi_spi_3/ip2intc_irpt
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ad_cpu_interconnect 0x44B80000 axi_spi_3
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