250 lines
8.1 KiB
Verilog
250 lines
8.1 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad9739a #(
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parameter ID = 0,
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parameter FPGA_TECHNOLOGY = 0,
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parameter FPGA_FAMILY = 0,
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parameter SPEED_GRADE = 0,
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parameter DEV_PACKAGE = 0,
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parameter SERDES_OR_DDR_N = 1,
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parameter MMCM_OR_BUFIO_N = 1,
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parameter DAC_DDS_TYPE = 2,
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parameter DAC_DDS_CORDIC_DW = 16,
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parameter DAC_DDS_CORDIC_PHASE_DW = 16,
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parameter DAC_DATAPATH_DISABLE = 0,
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parameter IO_DELAY_GROUP = "dev_if_delay_group") (
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// dac interface
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input dac_clk_in_p,
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input dac_clk_in_n,
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output dac_clk_out_p,
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output dac_clk_out_n,
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output [ 13:0] dac_data_out_a_p,
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output [ 13:0] dac_data_out_a_n,
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output [ 13:0] dac_data_out_b_p,
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output [ 13:0] dac_data_out_b_n,
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// dma interface
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output dac_div_clk,
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output dac_valid,
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output dac_enable,
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input [255:0] dac_ddata,
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input dac_dunf,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [ 15:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [ 31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [ 15:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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// internal clocks and resets
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wire dac_rst;
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wire up_clk;
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wire up_rstn;
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// internal signals
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wire [ 15:0] dac_data_00_s;
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wire [ 15:0] dac_data_01_s;
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wire [ 15:0] dac_data_02_s;
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wire [ 15:0] dac_data_03_s;
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wire [ 15:0] dac_data_04_s;
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wire [ 15:0] dac_data_05_s;
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wire [ 15:0] dac_data_06_s;
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wire [ 15:0] dac_data_07_s;
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wire [ 15:0] dac_data_08_s;
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wire [ 15:0] dac_data_09_s;
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wire [ 15:0] dac_data_10_s;
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wire [ 15:0] dac_data_11_s;
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wire [ 15:0] dac_data_12_s;
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wire [ 15:0] dac_data_13_s;
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wire [ 15:0] dac_data_14_s;
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wire [ 15:0] dac_data_15_s;
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wire dac_status_s;
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wire up_wreq_s;
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wire [ 13:0] up_waddr_s;
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wire [ 31:0] up_wdata_s;
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wire up_wack_s;
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wire up_rreq_s;
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wire [ 13:0] up_raddr_s;
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wire [ 31:0] up_rdata_s;
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wire up_rack_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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// device interface
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axi_ad9739a_if #(.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY)) i_if (
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.dac_clk_in_p (dac_clk_in_p),
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.dac_clk_in_n (dac_clk_in_n),
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.dac_clk_out_p (dac_clk_out_p),
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.dac_clk_out_n (dac_clk_out_n),
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.dac_data_out_a_p (dac_data_out_a_p),
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.dac_data_out_a_n (dac_data_out_a_n),
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.dac_data_out_b_p (dac_data_out_b_p),
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.dac_data_out_b_n (dac_data_out_b_n),
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.dac_rst (dac_rst),
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.dac_clk (),
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.dac_div_clk (dac_div_clk),
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.dac_status (dac_status_s),
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.dac_data_00 (dac_data_00_s),
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.dac_data_01 (dac_data_01_s),
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.dac_data_02 (dac_data_02_s),
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.dac_data_03 (dac_data_03_s),
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.dac_data_04 (dac_data_04_s),
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.dac_data_05 (dac_data_05_s),
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.dac_data_06 (dac_data_06_s),
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.dac_data_07 (dac_data_07_s),
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.dac_data_08 (dac_data_08_s),
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.dac_data_09 (dac_data_09_s),
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.dac_data_10 (dac_data_10_s),
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.dac_data_11 (dac_data_11_s),
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.dac_data_12 (dac_data_12_s),
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.dac_data_13 (dac_data_13_s),
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.dac_data_14 (dac_data_14_s),
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.dac_data_15 (dac_data_15_s));
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// core
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axi_ad9739a_core #(
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.ID(ID),
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.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
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.FPGA_FAMILY (FPGA_FAMILY),
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.SPEED_GRADE (SPEED_GRADE),
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.DEV_PACKAGE (DEV_PACKAGE),
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.DAC_DDS_TYPE (DAC_DDS_TYPE),
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.DAC_DDS_CORDIC_DW (DAC_DDS_CORDIC_DW),
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.DAC_DDS_CORDIC_PHASE_DW (DAC_DDS_CORDIC_PHASE_DW),
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.DATAPATH_DISABLE(DAC_DATAPATH_DISABLE))
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i_core (
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.dac_div_clk (dac_div_clk),
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.dac_rst (dac_rst),
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.dac_data_00 (dac_data_00_s),
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.dac_data_01 (dac_data_01_s),
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.dac_data_02 (dac_data_02_s),
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.dac_data_03 (dac_data_03_s),
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.dac_data_04 (dac_data_04_s),
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.dac_data_05 (dac_data_05_s),
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.dac_data_06 (dac_data_06_s),
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.dac_data_07 (dac_data_07_s),
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.dac_data_08 (dac_data_08_s),
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.dac_data_09 (dac_data_09_s),
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.dac_data_10 (dac_data_10_s),
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.dac_data_11 (dac_data_11_s),
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.dac_data_12 (dac_data_12_s),
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.dac_data_13 (dac_data_13_s),
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.dac_data_14 (dac_data_14_s),
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.dac_data_15 (dac_data_15_s),
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.dac_status (dac_status_s),
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.dac_valid (dac_valid),
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.dac_enable (dac_enable),
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.dac_ddata (dac_ddata),
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.dac_dunf (dac_dunf),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s),
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.up_rack (up_rack_s));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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